Merge patch series "ufs: Add support for AMD Versal Gen2 UFS"
Ajay Neeli <ajay.neeli@amd.com> says: This patch series adds support for the UFS driver on the AMD Versal Gen 2 SoC. It includes: - Device tree bindings and driver implementation. - Secure read support for the secure retrieval of UFS calibration values. The UFS host driver is based upon the Synopsis DesignWare (DWC) UFS architecture, utilizing the existing UFSHCD_DWC and UFSHCD_PLATFORM drivers. Link: https://patch.msgid.link/20251021113003.13650-1-ajay.neeli@amd.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Martin K. Petersen
61
Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml
Normal file
61
Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml
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@@ -0,0 +1,61 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/amd,versal2-ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: AMD Versal Gen 2 UFS Host Controller
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maintainers:
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- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
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allOf:
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- $ref: ufs-common.yaml
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properties:
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compatible:
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const: amd,versal2-ufs
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: core
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power-domains:
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maxItems: 1
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: host
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- const: phy
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required:
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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ufs@f10b0000 {
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compatible = "amd,versal2-ufs";
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reg = <0xf10b0000 0x1000>;
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clocks = <&ufs_core_clk>;
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clock-names = "core";
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resets = <&scmi_reset 4>, <&scmi_reset 35>;
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reset-names = "host", "phy";
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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freq-table-hz = <0 0>;
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};
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@@ -26339,6 +26339,13 @@ F: Documentation/devicetree/bindings/ufs/
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F: Documentation/scsi/ufs.rst
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F: drivers/ufs/core/
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UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER AMD VERSAL2
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M: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
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M: Ajay Neeli <ajay.neeli@amd.com>
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S: Maintained
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F: Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml
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F: drivers/ufs/host/ufs-amd-versal2.c
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UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER DWC HOOKS
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M: Pedro Sousa <pedrom.sousa@synopsys.com>
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L: linux-scsi@vger.kernel.org
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@@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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# Makefile for Xilinx firmwares
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obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o
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obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o zynqmp-ufs.o
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obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o
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118
drivers/firmware/xilinx/zynqmp-ufs.c
Normal file
118
drivers/firmware/xilinx/zynqmp-ufs.c
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@@ -0,0 +1,118 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Firmware Layer for UFS APIs
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*
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* Copyright (C) 2025 Advanced Micro Devices, Inc.
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*/
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#include <linux/firmware/xlnx-zynqmp.h>
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#include <linux/module.h>
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/* Register Node IDs */
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#define PM_REGNODE_PMC_IOU_SLCR 0x30000002 /* PMC IOU SLCR */
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#define PM_REGNODE_EFUSE_CACHE 0x30000003 /* EFUSE Cache */
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/* Register Offsets for PMC IOU SLCR */
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#define SRAM_CSR_OFFSET 0x104C /* SRAM Control and Status */
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#define TXRX_CFGRDY_OFFSET 0x1054 /* M-PHY TX-RX Config ready */
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/* Masks for SRAM Control and Status Register */
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#define SRAM_CSR_INIT_DONE_MASK BIT(0) /* SRAM initialization done */
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#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) /* SRAM External load done */
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#define SRAM_CSR_BYPASS_MASK BIT(2) /* Bypass SRAM interface */
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/* Mask to check M-PHY TX-RX configuration readiness */
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#define TX_RX_CFG_RDY_MASK GENMASK(3, 0)
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/* Register Offsets for EFUSE Cache */
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#define UFS_CAL_1_OFFSET 0xBE8 /* UFS Calibration Value */
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/**
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* zynqmp_pm_is_mphy_tx_rx_config_ready - check M-PHY TX-RX config readiness
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* @is_ready: Store output status (true/false)
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*
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* Return: Returns 0 on success or error value on failure.
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*/
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int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready)
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{
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u32 regval;
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int ret;
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if (!is_ready)
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return -EINVAL;
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ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, TXRX_CFGRDY_OFFSET, ®val);
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if (ret)
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return ret;
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regval &= TX_RX_CFG_RDY_MASK;
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if (regval)
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*is_ready = true;
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else
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*is_ready = false;
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_is_mphy_tx_rx_config_ready);
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/**
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* zynqmp_pm_is_sram_init_done - check SRAM initialization
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* @is_done: Store output status (true/false)
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*
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* Return: Returns 0 on success or error value on failure.
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*/
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int zynqmp_pm_is_sram_init_done(bool *is_done)
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{
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u32 regval;
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int ret;
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if (!is_done)
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return -EINVAL;
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ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, ®val);
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if (ret)
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return ret;
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regval &= SRAM_CSR_INIT_DONE_MASK;
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if (regval)
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*is_done = true;
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else
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*is_done = false;
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_is_sram_init_done);
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/**
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* zynqmp_pm_set_sram_bypass - Set SRAM bypass Control
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*
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* Return: Returns 0 on success or error value on failure.
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*/
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int zynqmp_pm_set_sram_bypass(void)
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{
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u32 sram_csr;
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int ret;
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ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, &sram_csr);
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if (ret)
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return ret;
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sram_csr &= ~SRAM_CSR_EXT_LD_DONE_MASK;
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sram_csr |= SRAM_CSR_BYPASS_MASK;
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return zynqmp_pm_sec_mask_write_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET,
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GENMASK(2, 1), sram_csr);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_set_sram_bypass);
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/**
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* zynqmp_pm_get_ufs_calibration_values - Read UFS calibration values
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* @val: Store the calibration value
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*
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* Return: Returns 0 on success or error value on failure.
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*/
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int zynqmp_pm_get_ufs_calibration_values(u32 *val)
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{
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return zynqmp_pm_sec_read_reg(PM_REGNODE_EFUSE_CACHE, UFS_CAL_1_OFFSET, val);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_get_ufs_calibration_values);
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@@ -1616,6 +1616,52 @@ int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
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return zynqmp_pm_invoke_fn(PM_IOCTL, payload, 3, 0, IOCTL_GET_FEATURE_CONFIG, id);
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}
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/**
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* zynqmp_pm_sec_read_reg - PM call to securely read from given offset
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* of the node
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* @node_id: Node Id of the device
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* @offset: Offset to be used (20-bit)
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* @ret_value: Output data read from the given offset after
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* firmware access policy is successfully enforced
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*
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* Return: Returns 0 on success or error value on failure
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*/
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int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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u32 count = 1;
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int ret;
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if (!ret_value)
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return -EINVAL;
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ret = zynqmp_pm_invoke_fn(PM_IOCTL, ret_payload, 4, node_id, IOCTL_READ_REG,
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offset, count);
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*ret_value = ret_payload[1];
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_sec_read_reg);
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/**
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* zynqmp_pm_sec_mask_write_reg - PM call to securely write to given offset
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* of the node
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* @node_id: Node Id of the device
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* @offset: Offset to be used (20-bit)
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* @mask: Mask to be used
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* @value: Value to be written
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*
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* Return: Returns 0 on success or error value on failure
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*/
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int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, u32 mask,
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u32 value)
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{
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return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 5, node_id, IOCTL_MASK_WRITE_REG,
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offset, mask, value);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_sec_mask_write_reg);
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/**
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* zynqmp_pm_set_sd_config - PM call to set value of SD config registers
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* @node: SD node ID
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@@ -154,3 +154,16 @@ config SCSI_UFS_ROCKCHIP
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Select this if you have UFS controller on Rockchip chipset.
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If unsure, say N.
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config SCSI_UFS_AMD_VERSAL2
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tristate "AMD Versal Gen 2 UFS controller platform driver"
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depends on SCSI_UFSHCD_PLATFORM && (ARCH_ZYNQMP || COMPILE_TEST)
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help
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This selects the AMD Versal Gen 2 specific additions on top of
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the UFSHCD DWC and UFSHCD platform driver. UFS host on AMD
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Versal Gen 2 needs some vendor specific configurations like PHY
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and vendor specific register accesses before accessing the
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hardware.
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Select this if you have UFS controller on AMD Versal Gen 2 SoC.
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If unsure, say N.
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@@ -13,3 +13,4 @@ obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o
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obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o
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obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o
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obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o
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obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o
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564
drivers/ufs/host/ufs-amd-versal2.c
Normal file
564
drivers/ufs/host/ufs-amd-versal2.c
Normal file
@@ -0,0 +1,564 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Advanced Micro Devices, Inc.
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*
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* Authors: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/firmware/xlnx-zynqmp.h>
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#include <linux/irqreturn.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <ufs/unipro.h>
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#include "ufshcd-dwc.h"
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#include "ufshcd-pltfrm.h"
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#include "ufshci-dwc.h"
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/* PHY modes */
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#define UFSHCD_DWC_PHY_MODE_ROM 0
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#define MPHY_FAST_RX_AFE_CAL BIT(2)
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#define MPHY_FW_CALIB_CFG_VAL BIT(8)
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#define MPHY_RX_OVRD_EN BIT(3)
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#define MPHY_RX_OVRD_VAL BIT(2)
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#define MPHY_RX_ACK_MASK BIT(0)
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#define TIMEOUT_MICROSEC 1000000
|
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struct ufs_versal2_host {
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struct ufs_hba *hba;
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struct reset_control *rstc;
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struct reset_control *rstphy;
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u32 phy_mode;
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unsigned long host_clk;
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u8 attcompval0;
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u8 attcompval1;
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u8 ctlecompval0;
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u8 ctlecompval1;
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};
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static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val)
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{
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static struct ufshcd_dme_attr_val phy_write_attrs[] = {
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{ UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL },
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{ UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL },
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{ UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL },
|
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{ UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL },
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{ UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL },
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{ UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
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};
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phy_write_attrs[0].mib_val = (u8)addr;
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phy_write_attrs[1].mib_val = (u8)(addr >> 8);
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phy_write_attrs[2].mib_val = (u8)val;
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phy_write_attrs[3].mib_val = (u8)(val >> 8);
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return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs));
|
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}
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static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val)
|
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{
|
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u32 mib_val;
|
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int ret;
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static struct ufshcd_dme_attr_val phy_read_attrs[] = {
|
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{ UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL },
|
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{ UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL },
|
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{ UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL },
|
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{ UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
|
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};
|
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phy_read_attrs[0].mib_val = (u8)addr;
|
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phy_read_attrs[1].mib_val = (u8)(addr >> 8);
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|
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ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs));
|
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if (ret)
|
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return ret;
|
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|
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val);
|
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if (ret)
|
||||
return ret;
|
||||
|
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*val = mib_val;
|
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val);
|
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if (ret)
|
||||
return ret;
|
||||
|
||||
*val |= (mib_val << 8);
|
||||
|
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return 0;
|
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}
|
||||
|
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static int ufs_versal2_enable_phy(struct ufs_hba *hba)
|
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{
|
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u32 offset, reg;
|
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int ret;
|
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|
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0);
|
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if (ret)
|
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return ret;
|
||||
|
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Check Tx/Rx FSM states */
|
||||
for (offset = 0; offset < 2; offset++) {
|
||||
u32 time_left, mibsel;
|
||||
|
||||
time_left = TIMEOUT_MICROSEC;
|
||||
mibsel = UIC_ARG_MIB_SEL(MTX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(offset));
|
||||
do {
|
||||
ret = ufshcd_dme_get(hba, mibsel, ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (reg == TX_STATE_HIBERN8 || reg == TX_STATE_SLEEP ||
|
||||
reg == TX_STATE_LSBURST)
|
||||
break;
|
||||
|
||||
time_left--;
|
||||
usleep_range(1, 5);
|
||||
} while (time_left);
|
||||
|
||||
if (!time_left) {
|
||||
dev_err(hba->dev, "Invalid Tx FSM state.\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
time_left = TIMEOUT_MICROSEC;
|
||||
mibsel = UIC_ARG_MIB_SEL(MRX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(offset));
|
||||
do {
|
||||
ret = ufshcd_dme_get(hba, mibsel, ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (reg == RX_STATE_HIBERN8 || reg == RX_STATE_SLEEP ||
|
||||
reg == RX_STATE_LSBURST)
|
||||
break;
|
||||
|
||||
time_left--;
|
||||
usleep_range(1, 5);
|
||||
} while (time_left);
|
||||
|
||||
if (!time_left) {
|
||||
dev_err(hba->dev, "Invalid Rx FSM state.\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ufs_versal2_setup_phy(struct ufs_hba *hba)
|
||||
{
|
||||
struct ufs_versal2_host *host = ufshcd_get_variant(hba);
|
||||
int ret;
|
||||
u32 reg;
|
||||
|
||||
/* Bypass RX-AFE offset calibrations (ATT/CTLE) */
|
||||
ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg |= MPHY_FAST_RX_AFE_CAL;
|
||||
ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg |= MPHY_FAST_RX_AFE_CAL;
|
||||
ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Program ATT and CTLE compensation values */
|
||||
if (host->attcompval0) {
|
||||
ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (host->attcompval1) {
|
||||
ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (host->ctlecompval0) {
|
||||
ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (host->ctlecompval1) {
|
||||
ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg |= MPHY_FW_CALIB_CFG_VAL;
|
||||
ret = ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg |= MPHY_FW_CALIB_CFG_VAL;
|
||||
return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg);
|
||||
}
|
||||
|
||||
static int ufs_versal2_phy_init(struct ufs_hba *hba)
|
||||
{
|
||||
struct ufs_versal2_host *host = ufshcd_get_variant(hba);
|
||||
u32 time_left;
|
||||
bool is_ready;
|
||||
int ret;
|
||||
static const struct ufshcd_dme_attr_val rmmi_attrs[] = {
|
||||
{ UIC_ARG_MIB(CBREFCLKCTRL2), CBREFREFCLK_GATE_OVR_EN, DME_LOCAL },
|
||||
{ UIC_ARG_MIB(CBCRCTRL), 1, DME_LOCAL },
|
||||
{ UIC_ARG_MIB(CBC10DIRECTCONF2), 1, DME_LOCAL },
|
||||
{ UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
|
||||
};
|
||||
|
||||
/* Wait for Tx/Rx config_rdy */
|
||||
time_left = TIMEOUT_MICROSEC;
|
||||
do {
|
||||
time_left--;
|
||||
ret = zynqmp_pm_is_mphy_tx_rx_config_ready(&is_ready);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!is_ready)
|
||||
break;
|
||||
|
||||
usleep_range(1, 5);
|
||||
} while (time_left);
|
||||
|
||||
if (!time_left) {
|
||||
dev_err(hba->dev, "Tx/Rx configuration signal busy.\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
ret = ufshcd_dwc_dme_set_attrs(hba, rmmi_attrs, ARRAY_SIZE(rmmi_attrs));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = reset_control_deassert(host->rstphy);
|
||||
if (ret) {
|
||||
dev_err(hba->dev, "ufsphy reset deassert failed, err = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Wait for SRAM init done */
|
||||
time_left = TIMEOUT_MICROSEC;
|
||||
do {
|
||||
time_left--;
|
||||
ret = zynqmp_pm_is_sram_init_done(&is_ready);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (is_ready)
|
||||
break;
|
||||
|
||||
usleep_range(1, 5);
|
||||
} while (time_left);
|
||||
|
||||
if (!time_left) {
|
||||
dev_err(hba->dev, "SRAM initialization failed.\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
ret = ufs_versal2_setup_phy(hba);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return ufs_versal2_enable_phy(hba);
|
||||
}
|
||||
|
||||
static int ufs_versal2_init(struct ufs_hba *hba)
|
||||
{
|
||||
struct ufs_versal2_host *host;
|
||||
struct device *dev = hba->dev;
|
||||
struct ufs_clk_info *clki;
|
||||
int ret;
|
||||
u32 cal;
|
||||
|
||||
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
host->hba = hba;
|
||||
ufshcd_set_variant(hba, host);
|
||||
|
||||
host->phy_mode = UFSHCD_DWC_PHY_MODE_ROM;
|
||||
|
||||
list_for_each_entry(clki, &hba->clk_list_head, list) {
|
||||
if (!strcmp(clki->name, "core"))
|
||||
host->host_clk = clk_get_rate(clki->clk);
|
||||
}
|
||||
|
||||
host->rstc = devm_reset_control_get_exclusive(dev, "host");
|
||||
if (IS_ERR(host->rstc)) {
|
||||
dev_err(dev, "failed to get reset ctrl: host\n");
|
||||
return PTR_ERR(host->rstc);
|
||||
}
|
||||
|
||||
host->rstphy = devm_reset_control_get_exclusive(dev, "phy");
|
||||
if (IS_ERR(host->rstphy)) {
|
||||
dev_err(dev, "failed to get reset ctrl: phy\n");
|
||||
return PTR_ERR(host->rstphy);
|
||||
}
|
||||
|
||||
ret = reset_control_assert(host->rstc);
|
||||
if (ret) {
|
||||
dev_err(hba->dev, "host reset assert failed, err = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_assert(host->rstphy);
|
||||
if (ret) {
|
||||
dev_err(hba->dev, "phy reset assert failed, err = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = zynqmp_pm_set_sram_bypass();
|
||||
if (ret) {
|
||||
dev_err(dev, "Bypass SRAM interface failed, err = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(host->rstc);
|
||||
if (ret)
|
||||
dev_err(hba->dev, "host reset deassert failed, err = %d\n", ret);
|
||||
|
||||
ret = zynqmp_pm_get_ufs_calibration_values(&cal);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to read calibration values\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
host->attcompval0 = (u8)cal;
|
||||
host->attcompval1 = (u8)(cal >> 8);
|
||||
host->ctlecompval0 = (u8)(cal >> 16);
|
||||
host->ctlecompval1 = (u8)(cal >> 24);
|
||||
|
||||
hba->quirks |= UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba,
|
||||
enum ufs_notify_change_status status)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (status == PRE_CHANGE) {
|
||||
ret = ufs_versal2_phy_init(hba);
|
||||
if (ret)
|
||||
dev_err(hba->dev, "Phy init failed (%d)\n", ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ufs_versal2_link_startup_notify(struct ufs_hba *hba,
|
||||
enum ufs_notify_change_status status)
|
||||
{
|
||||
struct ufs_versal2_host *host = ufshcd_get_variant(hba);
|
||||
int ret = 0;
|
||||
|
||||
switch (status) {
|
||||
case PRE_CHANGE:
|
||||
if (host->host_clk)
|
||||
ufshcd_writel(hba, host->host_clk / 1000000, DWC_UFS_REG_HCLKDIV);
|
||||
|
||||
break;
|
||||
case POST_CHANGE:
|
||||
ret = ufshcd_dwc_link_startup_notify(hba, status);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_req)
|
||||
{
|
||||
u32 time_left, reg, lane;
|
||||
int ret;
|
||||
|
||||
for (lane = 0; lane < activelanes; lane++) {
|
||||
time_left = TIMEOUT_MICROSEC;
|
||||
ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg |= MPHY_RX_OVRD_EN;
|
||||
if (rx_req)
|
||||
reg |= MPHY_RX_OVRD_VAL;
|
||||
else
|
||||
reg &= ~MPHY_RX_OVRD_VAL;
|
||||
|
||||
ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
do {
|
||||
ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg &= MPHY_RX_ACK_MASK;
|
||||
if (reg == rx_req)
|
||||
break;
|
||||
|
||||
time_left--;
|
||||
usleep_range(1, 5);
|
||||
} while (time_left);
|
||||
|
||||
if (!time_left) {
|
||||
dev_err(hba->dev, "Invalid Rx Ack value.\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_change_status status,
|
||||
const struct ufs_pa_layer_attr *dev_max_params,
|
||||
struct ufs_pa_layer_attr *dev_req_params)
|
||||
{
|
||||
struct ufs_versal2_host *host = ufshcd_get_variant(hba);
|
||||
u32 lane, reg, rate = 0;
|
||||
int ret = 0;
|
||||
|
||||
if (status == PRE_CHANGE) {
|
||||
memcpy(dev_req_params, dev_max_params, sizeof(struct ufs_pa_layer_attr));
|
||||
|
||||
/* If it is not a calibrated part, switch PWRMODE to SLOW_MODE */
|
||||
if (!host->attcompval0 && !host->attcompval1 && !host->ctlecompval0 &&
|
||||
!host->ctlecompval1) {
|
||||
dev_req_params->pwr_rx = SLOW_MODE;
|
||||
dev_req_params->pwr_tx = SLOW_MODE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (dev_req_params->pwr_rx == SLOW_MODE || dev_req_params->pwr_rx == SLOWAUTO_MODE)
|
||||
return 0;
|
||||
|
||||
if (dev_req_params->hs_rate == PA_HS_MODE_B)
|
||||
rate = 1;
|
||||
|
||||
/* Select the rate */
|
||||
ret = ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ufs_versal2_phy_ratesel(hba, dev_req_params->lane_tx, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ufs_versal2_phy_ratesel(hba, dev_req_params->lane_tx, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Remove rx_req override */
|
||||
for (lane = 0; lane < dev_req_params->lane_tx; lane++) {
|
||||
ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg &= ~MPHY_RX_OVRD_EN;
|
||||
ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (dev_req_params->lane_tx == UFS_LANE_2 && dev_req_params->lane_rx == UFS_LANE_2)
|
||||
ret = ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx,
|
||||
PA_INITIAL_ADAPT);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct ufs_hba_variant_ops ufs_versal2_hba_vops = {
|
||||
.name = "ufs-versal2-pltfm",
|
||||
.init = ufs_versal2_init,
|
||||
.link_startup_notify = ufs_versal2_link_startup_notify,
|
||||
.hce_enable_notify = ufs_versal2_hce_enable_notify,
|
||||
.pwr_change_notify = ufs_versal2_pwr_change_notify,
|
||||
};
|
||||
|
||||
static const struct of_device_id ufs_versal2_pltfm_match[] = {
|
||||
{
|
||||
.compatible = "amd,versal2-ufs",
|
||||
.data = &ufs_versal2_hba_vops,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ufs_versal2_pltfm_match);
|
||||
|
||||
static int ufs_versal2_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
||||
/* Perform generic probe */
|
||||
ret = ufshcd_pltfrm_init(pdev, &ufs_versal2_hba_vops);
|
||||
if (ret)
|
||||
dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ufs_versal2_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ufs_hba *hba = platform_get_drvdata(pdev);
|
||||
|
||||
pm_runtime_get_sync(&(pdev)->dev);
|
||||
ufshcd_remove(hba);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops ufs_versal2_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
|
||||
SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver ufs_versal2_pltfm = {
|
||||
.probe = ufs_versal2_probe,
|
||||
.remove = ufs_versal2_remove,
|
||||
.driver = {
|
||||
.name = "ufshcd-versal2",
|
||||
.pm = &ufs_versal2_pm_ops,
|
||||
.of_match_table = of_match_ptr(ufs_versal2_pltfm_match),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(ufs_versal2_pltfm);
|
||||
|
||||
MODULE_AUTHOR("Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>");
|
||||
MODULE_DESCRIPTION("AMD Versal Gen 2 UFS Host Controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -12,6 +12,52 @@
|
||||
|
||||
#include <ufs/ufshcd.h>
|
||||
|
||||
/* RMMI Attributes */
|
||||
#define CBREFCLKCTRL2 0x8132
|
||||
#define CBCRCTRL 0x811F
|
||||
#define CBC10DIRECTCONF2 0x810E
|
||||
#define CBRATESEL 0x8114
|
||||
#define CBCREGADDRLSB 0x8116
|
||||
#define CBCREGADDRMSB 0x8117
|
||||
#define CBCREGWRLSB 0x8118
|
||||
#define CBCREGWRMSB 0x8119
|
||||
#define CBCREGRDLSB 0x811A
|
||||
#define CBCREGRDMSB 0x811B
|
||||
#define CBCREGRDWRSEL 0x811C
|
||||
|
||||
#define CBREFREFCLK_GATE_OVR_EN BIT(7)
|
||||
|
||||
/* M-PHY Attributes */
|
||||
#define MTX_FSM_STATE 0x41
|
||||
#define MRX_FSM_STATE 0xC1
|
||||
|
||||
/* M-PHY registers */
|
||||
#define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100))
|
||||
#define RX_PCS_OUT(n) (0x300F + ((n) * 0x100))
|
||||
#define FAST_FLAGS(n) (0x401C + ((n) * 0x100))
|
||||
#define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100))
|
||||
#define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100))
|
||||
#define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100))
|
||||
|
||||
/* Tx/Rx FSM state */
|
||||
enum rx_fsm_state {
|
||||
RX_STATE_DISABLED = 0,
|
||||
RX_STATE_HIBERN8 = 1,
|
||||
RX_STATE_SLEEP = 2,
|
||||
RX_STATE_STALL = 3,
|
||||
RX_STATE_LSBURST = 4,
|
||||
RX_STATE_HSBURST = 5,
|
||||
};
|
||||
|
||||
enum tx_fsm_state {
|
||||
TX_STATE_DISABLED = 0,
|
||||
TX_STATE_HIBERN8 = 1,
|
||||
TX_STATE_SLEEP = 2,
|
||||
TX_STATE_STALL = 3,
|
||||
TX_STATE_LSBURST = 4,
|
||||
TX_STATE_HSBURST = 5,
|
||||
};
|
||||
|
||||
struct ufshcd_dme_attr_val {
|
||||
u32 attr_sel;
|
||||
u32 mib_val;
|
||||
|
||||
38
include/linux/firmware/xlnx-zynqmp-ufs.h
Normal file
38
include/linux/firmware/xlnx-zynqmp-ufs.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Firmware layer for UFS APIs.
|
||||
*
|
||||
* Copyright (c) 2025 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __FIRMWARE_XLNX_ZYNQMP_UFS_H__
|
||||
#define __FIRMWARE_XLNX_ZYNQMP_UFS_H__
|
||||
|
||||
#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
|
||||
int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready);
|
||||
int zynqmp_pm_is_sram_init_done(bool *is_done);
|
||||
int zynqmp_pm_set_sram_bypass(void);
|
||||
int zynqmp_pm_get_ufs_calibration_values(u32 *val);
|
||||
#else
|
||||
static inline int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int zynqmp_pm_is_sram_init_done(bool *is_done)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int zynqmp_pm_set_sram_bypass(void)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int zynqmp_pm_get_ufs_calibration_values(u32 *val)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FIRMWARE_XLNX_ZYNQMP_UFS_H__ */
|
||||
@@ -16,6 +16,7 @@
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/firmware/xlnx-zynqmp-ufs.h>
|
||||
|
||||
#define ZYNQMP_PM_VERSION_MAJOR 1
|
||||
#define ZYNQMP_PM_VERSION_MINOR 0
|
||||
@@ -241,6 +242,7 @@ enum pm_ioctl_id {
|
||||
IOCTL_GET_FEATURE_CONFIG = 27,
|
||||
/* IOCTL for Secure Read/Write Interface */
|
||||
IOCTL_READ_REG = 28,
|
||||
IOCTL_MASK_WRITE_REG = 29,
|
||||
/* Dynamic SD/GEM configuration */
|
||||
IOCTL_SET_SD_CONFIG = 30,
|
||||
IOCTL_SET_GEM_CONFIG = 31,
|
||||
@@ -619,6 +621,9 @@ int zynqmp_pm_feature(const u32 api_id);
|
||||
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
|
||||
int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
|
||||
int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
|
||||
int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value);
|
||||
int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset,
|
||||
u32 mask, u32 value);
|
||||
int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
|
||||
int zynqmp_pm_force_pwrdwn(const u32 target,
|
||||
const enum zynqmp_pm_request_ack ack);
|
||||
@@ -916,6 +921,17 @@ static inline int zynqmp_pm_request_wake(const u32 node,
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset,
|
||||
u32 mask, u32 value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
|
||||
{
|
||||
return -ENODEV;
|
||||
|
||||
@@ -179,6 +179,7 @@
|
||||
#define VS_POWERSTATE 0xD083
|
||||
#define VS_MPHYCFGUPDT 0xD085
|
||||
#define VS_DEBUGOMC 0xD09E
|
||||
#define VS_MPHYDISABLE 0xD0C1
|
||||
|
||||
#define PA_GRANULARITY_MIN_VAL 1
|
||||
#define PA_GRANULARITY_MAX_VAL 6
|
||||
|
||||
Reference in New Issue
Block a user