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dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC

"mss-top-sysreg" contains clocks, pinctrl, resets, an interrupt controller
and more. At this point, only the reset controller child is described as
that's all that is described by the existing bindings.
The clock controller already has a dedicated node, and will retain it as
there are other clock regions, so like the mailbox, a compatible-based
lookup of the syscon is sufficient to keep the clock driver working as
before, so no child is needed. There's also an interrupt multiplexing
service provided by this syscon, for which there is work in progress at
[1].

Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a4fefe@wendy/ [1]
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley
2025-10-13 18:45:33 +01:00
parent 3a86608788
commit feaa716adc

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description:
An wide assortment of registers that control elements of the MSS on PolarFire
SoC, including pinmuxing, resets and clocks among others.
properties:
compatible:
items:
- const: microchip,mpfs-mss-top-sysreg
- const: syscon
reg:
maxItems: 1
'#reset-cells':
description:
The AHB/AXI peripherals on the PolarFire SoC have reset support, so
from CLK_ENVM to CLK_CFM. The reset consumer should specify the
desired peripheral via the clock ID in its "resets" phandle cell.
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
of PolarFire clock/reset IDs.
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@20002000 {
compatible = "microchip,mpfs-mss-top-sysreg", "syscon";
reg = <0x20002000 0x1000>;
#reset-cells = <1>;
};