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arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board

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Add device tree support for the Black Sesame Technologies (BST) C1200
CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC
family.
The changes include:
- Adding a new BST device tree directory
- Adding Makefile entries to build the BST platform device trees
- Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board
This board features a quad-core Cortex-A78 CPU, and various peripherals
including UART, and interrupt controller.

Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Albert Yang
2025-10-16 20:05:56 +08:00
committed by Arnd Bergmann
parent 1541219416
commit c03a37773b
4 changed files with 124 additions and 0 deletions
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1
arch/arm64/boot/dts/Makefile
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@@ -13,6 +13,7 @@ subdir-y += axiado
subdir-y += bitmain
subdir-y += blaize
subdir-y += broadcom
subdir-y += bst
subdir-y += cavium
subdir-y += cix
subdir-y += exynos

2
arch/arm64/boot/dts/bst/Makefile Normal file
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@@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb

24
arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts Normal file
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@@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bstc1200.dtsi"
/ {
model = "BST C1200-96 CDCU1.0 4C2G";
compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200";
chosen {
stdout-path = "serial0:115200n8";
};
memory@810000000 {
device_type = "memory";
reg = <0x8 0x10000000 0x0 0x30000000>,
<0x8 0xc0000000 0x1 0x0>,
<0xc 0x00000000 0x0 0x40000000>;
};
};
&uart0 {
status = "okay";
};

97
arch/arm64/boot/dts/bst/bstc1200.dtsi Normal file
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@@ -0,0 +1,97 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "bst,c1200";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_cache>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x100>;
enable-method = "psci";
next-level-cache = <&l2_cache>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x200>;
enable-method = "psci";
next-level-cache = <&l2_cache>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x300>;
enable-method = "psci";
next-level-cache = <&l2_cache>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc {
compatible = "simple-bus";
ranges;
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
uart0: serial@20008000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x20008000 0x0 0x1000>;
clock-frequency = <25000000>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
gic: interrupt-controller@32800000 {
compatible = "arm,gic-v3";
reg = <0x0 0x32800000 0x0 0x10000>,
<0x0 0x32880000 0x0 0x100000>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
};
timer {
compatible = "arm,armv8-timer";
always-on;
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};