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[PATCH] x86_64: Set ____cacheline_maxaligned_in_smp alignment to 128 bytes

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The current value was correct before the introduction of Intel EM64T support -
but now L1_CACHE_SHIFT_MAX can be less than L1_CACHE_SHIFT, which _is_ funny!

Between the few users of ____cacheline_maxaligned_in_smp, we also have (for
example) rcu_ctrlblk, and struct zone, with zone->{lru_,}lock.  I.e.  we have
a lot of excess cacheline bouncing on them.

No correctness issues, obviously.  So this could even be merged for 2.6.14
(I'm not a fan of this idea, though).

CC: Andi Kleen <ak@suse.de>
Signed-off-by: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Paolo 'Blaisorblade' Giarrusso
2005-11-05 17:25:54 +01:00
committed by Linus Torvalds
parent 8e0d4f4e91
commit bf0f2e2383
1 changed files with 1 additions and 1 deletions
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2
include/asm-x86_64/cache.h
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@@ -9,6 +9,6 @@
/* L1 cache line size */
#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define L1_CACHE_SHIFT_MAX 6 /* largest L1 which this arch supports */
#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
#endif