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Merge tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/newsoc

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Initial Anlogic Platform Support

Add bindings for the serial and timer peripherals, and a basic soc dtsi
for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board
for this SoC. Add myself as maintainer for this platform for the time
being.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  MAINTAINERS: Setup support for Anlogic tree
  riscv: defconfig: Enable Anlogic SoC
  riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
  riscv: dts: Add initial Anlogic DR1V90 SoC device tree
  riscv: Add Anlogic SoC famly Kconfig support
  dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
  dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
  dt-bindings: riscv: Add Anlogic DR1V90
  dt-bindings: riscv: Add Nuclei UX900 compatibles
  dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
This commit is contained in:
Arnd Bergmann
2025-11-21 21:29:57 +01:00
parent c5dc31b2b4 d5c3f49b75
commit 9b418a3bfd
12 changed files with 191 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
Documentation/devicetree/bindings/riscv/anlogic.yaml Normal file
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@@ -0,0 +1,27 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/anlogic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Anlogic SoC-based boards
maintainers:
- Junhui Liu <junhui.liu@pigmoral.tech>
description:
Anlogic SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- milianke,mlkpai-fs01
- const: anlogic,dr1v90
additionalProperties: true
...

1
Documentation/devicetree/bindings/riscv/cpus.yaml
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@@ -48,6 +48,7 @@ properties:
- amd,mbv64
- andestech,ax45mp
- canaan,k210
- nuclei,ux900
- sifive,bullet0
- sifive,e5
- sifive,e7

1
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
View File

@@ -51,6 +51,7 @@ properties:
- const: renesas,rzn1-uart
- items:
- enum:
- anlogic,dr1v90-uart
- brcm,bcm11351-dw-apb-uart
- brcm,bcm21664-dw-apb-uart
- rockchip,px30-uart

17
Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
View File

@@ -4,18 +4,23 @@
$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo CLINT Timer
title: ACLINT Machine-level Timer Device
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
items:
- enum:
- sophgo,sg2042-aclint-mtimer
- sophgo,sg2044-aclint-mtimer
- const: thead,c900-aclint-mtimer
oneOf:
- items:
- enum:
- sophgo,sg2042-aclint-mtimer
- sophgo,sg2044-aclint-mtimer
- const: thead,c900-aclint-mtimer
- items:
- enum:
- anlogic,dr1v90-aclint-mtimer
- const: nuclei,ux900-aclint-mtimer
reg:
items:

6
Documentation/devicetree/bindings/vendor-prefixes.yaml
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@@ -132,6 +132,8 @@ patternProperties:
description: Anbernic
"^andestech,.*":
description: Andes Technology Corporation
"^anlogic,.*":
description: Shanghai Anlogic Infotech Co., Ltd.
"^anvo,.*":
description: Anvo-Systems Dresden GmbH
"^aoly,.*":
@@ -1025,6 +1027,8 @@ patternProperties:
description: MikroElektronika d.o.o.
"^mikrotik,.*":
description: MikroTik
"^milianke,.*":
description: Changzhou Milianke Electronic Technology Co., Ltd
"^milkv,.*":
description: MilkV Technology Co., Ltd
"^miniand,.*":
@@ -1142,6 +1146,8 @@ patternProperties:
description: Novatek
"^novtech,.*":
description: NovTech, Inc.
"^nuclei,.*":
description: Nuclei System Technology
"^numonyx,.*":
description: Numonyx (deprecated, use micron)
deprecated: true

8
MAINTAINERS
View File

@@ -22089,6 +22089,14 @@ F: Documentation/devicetree/bindings/riscv/andes.yaml
F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
F: arch/riscv/boot/dts/andes/
RISC-V ANLOGIC SoC SUPPORT
M: Conor Dooley <conor@kernel.org>
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
L: linux-riscv@lists.infradead.org
S: Odd Fixes
F: Documentation/devicetree/bindings/riscv/anlogic.yaml
F: arch/riscv/boot/dts/anlogic/
RISC-V ARCHITECTURE
M: Paul Walmsley <pjw@kernel.org>
M: Palmer Dabbelt <palmer@dabbelt.com>

5
arch/riscv/Kconfig.socs
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@@ -7,6 +7,11 @@ config ARCH_ANDES
help
This enables support for Andes SoC platform hardware.
config ARCH_ANLOGIC
bool "Anlogic SoCs"
help
This enables support for Anlogic SoC platform hardware.
config ARCH_ESWIN
bool "ESWIN SoCs"
help

1
arch/riscv/boot/dts/Makefile
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@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += allwinner
subdir-y += andes
subdir-y += anlogic
subdir-y += canaan
subdir-y += eswin
subdir-y += microchip

2
arch/riscv/boot/dts/anlogic/Makefile Normal file
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@@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb

28
arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts Normal file
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@@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
*/
#include "dr1v90.dtsi"
/ {
model = "Milianke MLKPAI-FS01";
compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90";
aliases {
serial0 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x20000000>;
};
};
&uart1 {
status = "okay";
};

100
arch/riscv/boot/dts/anlogic/dr1v90.dtsi Normal file
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@@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Anlogic DR1V90";
compatible = "anlogic,dr1v90";
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <800000000>;
cpu@0 {
compatible = "nuclei,ux900", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <256>;
d-cache-size = <32768>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <256>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
reg = <0>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
"zbkc", "zbs", "zicntr", "zicsr", "zifencei",
"zihintpause", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
aclint_mswi: interrupt-controller@68031000 {
compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
reg = <0x0 0x68031000 0x0 0x4000>;
interrupts-extended = <&cpu0_intc 3>;
};
aclint_mtimer: timer@68035000 {
compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
reg = <0x0 0x68035000 0x0 0x8000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu0_intc 7>;
};
aclint_sswi: interrupt-controller@6803d000 {
compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
reg = <0x0 0x6803d000 0x0 0x3000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 1>;
};
plic: interrupt-controller@6c000000 {
compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
reg = <0x0 0x6c000000 0x0 0x4000000>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
riscv,ndev = <150>;
};
uart0: serial@f8400000 {
compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
reg = <0x0 0xf8400000 0x0 0x1000>;
clock-frequency = <50000000>;
interrupts = <71>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart1: serial@f8401000 {
compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
reg = <0x0 0xf8401000 0x0 0x1000>;
clock-frequency = <50000000>;
interrupts = <72>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
};
};

1
arch/riscv/configs/defconfig
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@@ -23,6 +23,7 @@ CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
CONFIG_ARCH_ANDES=y
CONFIG_ARCH_ANLOGIC=y
CONFIG_ARCH_MICROCHIP=y
CONFIG_ARCH_SIFIVE=y
CONFIG_ARCH_SOPHGO=y