sugar/linux
1
0
Fork 0
Code Activity

Merge tag 'qcom-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers

Browse Source 
Qualcomm driver updates for v6.19

Support for hardware-keymanager v1 support for wrapped keys is introduce
in the ICE driver.

Support for the new Kaanapali mobile platform is added to last-level
cache controller, pd-mapper, and UBWC drivers.

UBWC driver gains support for the Monaco and Glymur platforms.

The PMIC GLINK driver is extended to handle the differences found in
targets where the related firmware runs on the SoCCP.

Support for running on targets without initialized SMEM is provided, by
reworking the SMEM driver to differentiate between "not yet probed" and
"probed but there was no SMEM". An unwanted WARN_ON() that triggered if
clients asked for a SMEM item beyond the currently running system's
limit, was removed, to allow new use cases to gracefully fail on old
targets.

The Qualcomm socinfo driver is extended with support for version 20
through 23 and support for providing version information about more than
32 remote processors. Identifiers for QCS6490 and SM8850 are also added.

Additionally, a number of smaller bug fixes and cleanups in PBS, OCMEM,
GSBI, TZMEM, and MDT-loader are included.

* tag 'qcom-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (31 commits)
  soc: qcom: mdt_loader: rename 'firmware' parameter of qcom_mdt_load()
  soc: qcom: mdt_loader: merge __qcom_mdt_load() and qcom_mdt_load_no_init()
  soc: qcom: socinfo: Add reserve field to support future extension
  soc: qcom: socinfo: Add support for new fields in revision 20
  dt-bindings: firmware: qcom,scm: Document SCM on Kaanapali SOC
  soc: qcom: socinfo: add support to extract more than 32 image versions
  soc: qcom: smem: drop the WARN_ON() on SMEM item validation
  soc: qcom: ubwc: Add config for Kaanapali
  soc: qcom: socinfo: Add SoC ID for QCS6490
  dt-bindings: arm: qcom,ids: Add SoC ID for QCS6490
  soc: qcom: ice: Add HWKM v1 support for wrapped keys
  soc: qcom: smem: better track SMEM uninitialized state
  err.h: add INIT_ERR_PTR() macro
  soc: qcom: smem: fix hwspinlock resource leak in probe error paths
  dt-bindings: soc: qcom,aoss-qmp: Document the Glymur AOSS side channel
  dt-bindings: soc: qcom,aoss-qmp: Document the Kaanapali AOSS channel
  soc: qcom: ubwc: Add QCS8300 UBWC cfg
  dt-bindings: firmware: qcom,scm: Document Glymur scm
  soc: qcom: socinfo: Add SM8850 SoC ID
  dt-bindings: arm: qcom,ids: Add SoC ID for SM8850
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-25 14:00:48 +01:00
parent a677d87689 186b8f8fcc
commit 3d497bf8ef
20 changed files with 647 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/cache/qcom,llcc.yaml vendored
View File

@@ -21,6 +21,7 @@ properties:
compatible:
enum:
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,qcs615-llcc
- qcom,qcs8300-llcc
- qcom,qdu1000-llcc
@@ -272,6 +273,7 @@ allOf:
compatible:
contains:
enum:
- qcom,kaanapali-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc

3
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
View File

@@ -23,6 +23,7 @@ properties:
- enum:
- qcom,scm-apq8064
- qcom,scm-apq8084
- qcom,scm-glymur
- qcom,scm-ipq4019
- qcom,scm-ipq5018
- qcom,scm-ipq5332
@@ -31,6 +32,7 @@ properties:
- qcom,scm-ipq806x
- qcom,scm-ipq8074
- qcom,scm-ipq9574
- qcom,scm-kaanapali
- qcom,scm-mdm9607
- qcom,scm-milos
- qcom,scm-msm8226
@@ -202,6 +204,7 @@ allOf:
compatible:
contains:
enum:
- qcom,scm-kaanapali
- qcom,scm-milos
- qcom,scm-sm8450
- qcom,scm-sm8550

2
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
View File

@@ -25,6 +25,8 @@ properties:
compatible:
items:
- enum:
- qcom,glymur-aoss-qmp
- qcom,kaanapali-aoss-qmp
- qcom,milos-aoss-qmp
- qcom,qcs615-aoss-qmp
- qcom,qcs8300-aoss-qmp

81
drivers/soc/qcom/ice.c
View File

@@ -22,7 +22,18 @@
#include <soc/qcom/ice.h>
#define AES_256_XTS_KEY_SIZE 64 /* for raw keys only */
#define QCOM_ICE_HWKM_WRAPPED_KEY_SIZE 100 /* assuming HWKM v2 */
#define QCOM_ICE_HWKM_V1 1 /* HWKM version 1 */
#define QCOM_ICE_HWKM_V2 2 /* HWKM version 2 */
#define QCOM_ICE_HWKM_MAX_WRAPPED_KEY_SIZE 100 /* Maximum HWKM wrapped key size */
/*
* Wrapped key size depends upon HWKM version:
* HWKM version 1 supports 68 bytes
* HWKM version 2 supports 100 bytes
*/
#define QCOM_ICE_HWKM_WRAPPED_KEY_SIZE(v) ((v) == QCOM_ICE_HWKM_V1 ? 68 : 100)
/* QCOM ICE registers */
@@ -62,13 +73,15 @@ union crypto_cfg {
#define QCOM_ICE_REG_HWKM_TZ_KM_CTL (HWKM_OFFSET + 0x1000)
#define QCOM_ICE_HWKM_DISABLE_CRC_CHECKS_VAL (BIT(1) | BIT(2))
/* In HWKM v1 the ICE legacy mode is controlled from HWKM register space */
#define QCOM_ICE_HWKM_ICE_LEGACY_MODE_ENABLED BIT(5)
#define QCOM_ICE_REG_HWKM_TZ_KM_STATUS (HWKM_OFFSET + 0x1004)
#define QCOM_ICE_HWKM_KT_CLEAR_DONE BIT(0)
#define QCOM_ICE_HWKM_BOOT_CMD_LIST0_DONE BIT(1)
#define QCOM_ICE_HWKM_BOOT_CMD_LIST1_DONE BIT(2)
#define QCOM_ICE_HWKM_CRYPTO_BIST_DONE_V2 BIT(7)
#define QCOM_ICE_HWKM_BIST_DONE_V2 BIT(9)
#define QCOM_ICE_HWKM_CRYPTO_BIST_DONE(v) (((v) == QCOM_ICE_HWKM_V1) ? BIT(14) : BIT(7))
#define QCOM_ICE_HWKM_BIST_DONE(v) (((v) == QCOM_ICE_HWKM_V1) ? BIT(16) : BIT(9))
#define QCOM_ICE_REG_HWKM_BANK0_BANKN_IRQ_STATUS (HWKM_OFFSET + 0x2008)
#define QCOM_ICE_HWKM_RSP_FIFO_CLEAR_VAL BIT(3)
@@ -97,6 +110,7 @@ struct qcom_ice {
struct clk *core_clk;
bool use_hwkm;
bool hwkm_init_complete;
u8 hwkm_version;
};
static bool qcom_ice_check_supported(struct qcom_ice *ice)
@@ -114,9 +128,24 @@ static bool qcom_ice_check_supported(struct qcom_ice *ice)
return false;
}
/* HWKM version v2 is present from ICE 3.2.1 onwards while version v1
* is present only in ICE 3.2.0. Earlier ICE version don't have HWKM.
*/
if (major > 3 ||
(major == 3 && (minor >= 3 || (minor == 2 && step >= 1))))
ice->hwkm_version = QCOM_ICE_HWKM_V2;
else if ((major == 3) && (minor == 2))
ice->hwkm_version = QCOM_ICE_HWKM_V1;
else
ice->hwkm_version = 0;
dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
major, minor, step);
if (ice->hwkm_version)
dev_info(dev, "QC Hardware Key Manager (HWKM) version v%d\n",
ice->hwkm_version);
/* If fuses are blown, ICE might not work in the standard way. */
regval = qcom_ice_readl(ice, QCOM_ICE_REG_FUSE_SETTING);
if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
@@ -131,19 +160,18 @@ static bool qcom_ice_check_supported(struct qcom_ice *ice)
* v3.2.1 and later have HWKM v2. ICE v3.2.0 has HWKM v1. Earlier ICE
* versions don't have HWKM at all. However, for HWKM to be fully
* usable by Linux, the TrustZone software also needs to support certain
* SCM calls including the ones to generate and prepare keys. That
* effectively makes the earliest supported SoC be SM8650, which has
* HWKM v2. Therefore, this driver doesn't include support for HWKM v1,
* and it checks for the SCM call support before it decides to use HWKM.
* SCM calls including the ones to generate and prepare keys. Support
* for these SCM calls is present for SoCs with HWKM v2 and is being
* added for SoCs with HWKM v1 as well but not every SoC with HWKM v1
* currently supports this. So, this driver checks for the SCM call
* support before it decides to use HWKM.
*
* Also, since HWKM and legacy mode are mutually exclusive, and
* ICE-capable storage driver(s) need to know early on whether to
* advertise support for raw keys or wrapped keys, HWKM cannot be used
* unconditionally. A module parameter is used to opt into using it.
*/
if ((major >= 4 ||
(major == 3 && (minor >= 3 || (minor == 2 && step >= 1)))) &&
qcom_scm_has_wrapped_key_support()) {
if (ice->hwkm_version && qcom_scm_has_wrapped_key_support()) {
if (qcom_ice_use_wrapped_keys) {
dev_info(dev, "Using HWKM. Supporting wrapped keys only.\n");
ice->use_hwkm = true;
@@ -212,8 +240,8 @@ static int qcom_ice_wait_bist_status(struct qcom_ice *ice)
(QCOM_ICE_HWKM_KT_CLEAR_DONE |
QCOM_ICE_HWKM_BOOT_CMD_LIST0_DONE |
QCOM_ICE_HWKM_BOOT_CMD_LIST1_DONE |
QCOM_ICE_HWKM_CRYPTO_BIST_DONE_V2 |
QCOM_ICE_HWKM_BIST_DONE_V2)) {
QCOM_ICE_HWKM_CRYPTO_BIST_DONE(ice->hwkm_version) |
QCOM_ICE_HWKM_BIST_DONE(ice->hwkm_version))) {
dev_err(ice->dev, "HWKM self-test error!\n");
/*
* Too late to revoke use_hwkm here, as it was already
@@ -230,7 +258,7 @@ static void qcom_ice_hwkm_init(struct qcom_ice *ice)
if (!ice->use_hwkm)
return;
BUILD_BUG_ON(QCOM_ICE_HWKM_WRAPPED_KEY_SIZE >
BUILD_BUG_ON(QCOM_ICE_HWKM_MAX_WRAPPED_KEY_SIZE >
BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE);
/*
* When ICE is in HWKM mode, it only supports wrapped keys.
@@ -238,9 +266,15 @@ static void qcom_ice_hwkm_init(struct qcom_ice *ice)
*
* Put ICE in HWKM mode. ICE defaults to legacy mode.
*/
regval = qcom_ice_readl(ice, QCOM_ICE_REG_CONTROL);
regval &= ~QCOM_ICE_LEGACY_MODE_ENABLED;
qcom_ice_writel(ice, regval, QCOM_ICE_REG_CONTROL);
if (ice->hwkm_version == QCOM_ICE_HWKM_V2) {
regval = qcom_ice_readl(ice, QCOM_ICE_REG_CONTROL);
regval &= ~QCOM_ICE_LEGACY_MODE_ENABLED;
qcom_ice_writel(ice, regval, QCOM_ICE_REG_CONTROL);
} else if (ice->hwkm_version == QCOM_ICE_HWKM_V1) {
regval = qcom_ice_readl(ice, QCOM_ICE_REG_HWKM_TZ_KM_CTL);
regval &= ~QCOM_ICE_HWKM_ICE_LEGACY_MODE_ENABLED;
qcom_ice_writel(ice, regval, QCOM_ICE_REG_HWKM_TZ_KM_CTL);
}
/* Disable CRC checks. This HWKM feature is not used. */
qcom_ice_writel(ice, QCOM_ICE_HWKM_DISABLE_CRC_CHECKS_VAL,
@@ -298,7 +332,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_suspend);
static unsigned int translate_hwkm_slot(struct qcom_ice *ice, unsigned int slot)
{
return slot * 2;
return ice->hwkm_version == QCOM_ICE_HWKM_V1 ? slot : slot * 2;
}
static int qcom_ice_program_wrapped_key(struct qcom_ice *ice, unsigned int slot,
@@ -451,11 +485,12 @@ int qcom_ice_generate_key(struct qcom_ice *ice,
{
int err;
err = qcom_scm_generate_ice_key(lt_key, QCOM_ICE_HWKM_WRAPPED_KEY_SIZE);
err = qcom_scm_generate_ice_key(lt_key,
QCOM_ICE_HWKM_WRAPPED_KEY_SIZE(ice->hwkm_version));
if (err)
return err;
return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE;
return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE(ice->hwkm_version);
}
EXPORT_SYMBOL_GPL(qcom_ice_generate_key);
@@ -478,13 +513,13 @@ int qcom_ice_prepare_key(struct qcom_ice *ice,
int err;
err = qcom_scm_prepare_ice_key(lt_key, lt_key_size,
eph_key, QCOM_ICE_HWKM_WRAPPED_KEY_SIZE);
eph_key, QCOM_ICE_HWKM_WRAPPED_KEY_SIZE(ice->hwkm_version));
if (err == -EIO || err == -EINVAL)
err = -EBADMSG; /* probably invalid key */
if (err)
return err;
return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE;
return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE(ice->hwkm_version);
}
EXPORT_SYMBOL_GPL(qcom_ice_prepare_key);
@@ -506,11 +541,11 @@ int qcom_ice_import_key(struct qcom_ice *ice,
int err;
err = qcom_scm_import_ice_key(raw_key, raw_key_size,
lt_key, QCOM_ICE_HWKM_WRAPPED_KEY_SIZE);
lt_key, QCOM_ICE_HWKM_WRAPPED_KEY_SIZE(ice->hwkm_version));
if (err)
return err;
return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE;
return QCOM_ICE_HWKM_WRAPPED_KEY_SIZE(ice->hwkm_version);
}
EXPORT_SYMBOL_GPL(qcom_ice_import_key);

373
drivers/soc/qcom/llcc-qcom.c
View File

@@ -214,6 +214,364 @@ static const struct llcc_slice_config ipq5424_data[] = {
},
};
static const struct llcc_slice_config kaanapali_data[] = {
{
.usecase_id = LLCC_CPUSS,
.slice_id = 1,
.max_cap = 5120,
.priority = 1,
.bonus_ways = 0xffffffff,
.activate_on_init = true,
.write_scid_en = true,
.stale_en = true,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_VIDSC0,
.slice_id = 2,
.max_cap = 512,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_AUDIO,
.slice_id = 35,
.max_cap = 512,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_MDMHPGRW,
.slice_id = 25,
.max_cap = 1024,
.priority = 5,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CMPT,
.slice_id = 34,
.max_cap = 4096,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_GPUHTW,
.slice_id = 11,
.max_cap = 512,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_GPU,
.slice_id = 9,
.max_cap = 5632,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.write_scid_cacheable_en = true,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_MMUHWT,
.slice_id = 18,
.max_cap = 768,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.activate_on_init = true,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_DISP,
.slice_id = 16,
.max_cap = 7168,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.cache_mode = 2,
.stale_en = true,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_MDMHPFX,
.slice_id = 24,
.max_cap = 1024,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_MDMPNG,
.slice_id = 27,
.max_cap = 256,
.priority = 5,
.bonus_ways = 0xfffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CVP,
.slice_id = 8,
.max_cap = 800,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_MODPE,
.slice_id = 29,
.max_cap = 256,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xf0000000,
.mru_uncap_en = true,
.alloc_oneway_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_WRCACHE,
.slice_id = 31,
.max_cap = 512,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.activate_on_init = true,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CVPFW,
.slice_id = 19,
.max_cap = 512,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_CPUMTE,
.slice_id = 7,
.max_cap = 256,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CMPTHCP,
.slice_id = 15,
.max_cap = 256,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_LCPDARE,
.slice_id = 30,
.max_cap = 128,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.activate_on_init = true,
.mru_uncap_en = true,
.alloc_oneway_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_AENPU,
.slice_id = 3,
.max_cap = 3072,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.cache_mode = 2,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_ISLAND1,
.slice_id = 12,
.max_cap = 7936,
.priority = 7,
.fixed_size = true,
.bonus_ways = 0x7fffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_DISP_WB,
.slice_id = 23,
.max_cap = 512,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_VIDVSP,
.slice_id = 4,
.max_cap = 256,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_VIDDEC,
.slice_id = 5,
.max_cap = 512,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.cache_mode = 2,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_CAMOFE,
.slice_id = 33,
.max_cap = 6144,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.stale_en = true,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_CAMRTIP,
.slice_id = 13,
.max_cap = 6144,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.stale_en = true,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_CAMRTRF,
.slice_id = 10,
.max_cap = 3584,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.stale_en = true,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_CAMSRTRF,
.slice_id = 21,
.max_cap = 6144,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.stale_en = true,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_VIDEO_APV,
.slice_id = 6,
.max_cap = 768,
.priority = 4,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_COMPUTE1,
.slice_id = 22,
.max_cap = 4096,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CPUSS_OPP,
.slice_id = 32,
.max_cap = 0,
.priority = 0,
.fixed_size = true,
.bonus_ways = 0,
.activate_on_init = true,
.write_scid_en = true,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CPUSSMPAM,
.slice_id = 17,
.max_cap = 2048,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.activate_on_init = true,
.write_scid_en = true,
.stale_en = true,
.mru_uncap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CAM_IPE_STROV,
.slice_id = 14,
.max_cap = 400,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_CAM_OFE_STROV,
.slice_id = 20,
.max_cap = 400,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0xffffffff,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
.parent_slice_id = 33,
}, {
.usecase_id = LLCC_CPUSS_HEU,
.slice_id = 28,
.max_cap = 0,
.priority = 0,
.fixed_size = true,
.bonus_ways = 0,
.mru_uncap_en = true,
.ovcap_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_MDM_PNG_FIXED,
.slice_id = 26,
.max_cap = 256,
.priority = 5,
.fixed_size = true,
.bonus_ways = 0xff000000,
.activate_on_init = true,
.write_scid_en = true,
.mru_uncap_en = true,
.vict_prio = true,
},
};
static const struct llcc_slice_config sa8775p_data[] = {
{
.usecase_id = LLCC_CPUSS,
@@ -3505,6 +3863,15 @@ static const u32 llcc_v6_reg_offset[] = {
[LLCC_TRP_WRS_CACHEABLE_EN] = 0x00042088,
};
static const struct qcom_llcc_config kaanapali_cfg[] = {
{
.sct_data = kaanapali_data,
.size = ARRAY_SIZE(kaanapali_data),
.reg_offset = llcc_v6_reg_offset,
.edac_reg_offset = &llcc_v6_edac_reg_offset,
},
};
static const struct qcom_llcc_config qcs615_cfg[] = {
{
.sct_data = qcs615_data,
@@ -3731,6 +4098,11 @@ static const struct qcom_llcc_config x1e80100_cfg[] = {
},
};
static const struct qcom_sct_config kaanapali_cfgs = {
.llcc_config = kaanapali_cfg,
.num_config = ARRAY_SIZE(kaanapali_cfg),
};
static const struct qcom_sct_config qcs615_cfgs = {
.llcc_config = qcs615_cfg,
.num_config = ARRAY_SIZE(qcs615_cfg),
@@ -4570,6 +4942,7 @@ err:
static const struct of_device_id qcom_llcc_of_match[] = {
{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
{ .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs},
{ .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs},
{ .compatible = "qcom,qcs8300-llcc", .data = &qcs8300_cfgs},
{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},

52
drivers/soc/qcom/mdt_loader.c
View File

@@ -332,10 +332,22 @@ static bool qcom_mdt_bins_are_split(const struct firmware *fw)
return false;
}
static int __qcom_mdt_load(struct device *dev, const struct firmware *fw,
const char *fw_name, void *mem_region,
phys_addr_t mem_phys, size_t mem_size,
phys_addr_t *reloc_base)
/**
* qcom_mdt_load_no_init() - load the firmware which header is loaded as fw
* @dev: device handle to associate resources with
* @fw: firmware object for the mdt file
* @fw_name: name of the firmware, for construction of segment file names
* @mem_region: allocated memory region to load firmware into
* @mem_phys: physical address of allocated memory region
* @mem_size: size of the allocated memory region
* @reloc_base: adjusted physical address after relocation
*
* Returns 0 on success, negative errno otherwise.
*/
int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
const char *fw_name, void *mem_region,
phys_addr_t mem_phys, size_t mem_size,
phys_addr_t *reloc_base)
{
const struct elf32_phdr *phdrs;
const struct elf32_phdr *phdr;
@@ -435,12 +447,13 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw,
return ret;
}
EXPORT_SYMBOL_GPL(qcom_mdt_load_no_init);
/**
* qcom_mdt_load() - load the firmware which header is loaded as fw
* @dev: device handle to associate resources with
* @fw: firmware object for the mdt file
* @firmware: name of the firmware, for construction of segment file names
* @fw_name: name of the firmware, for construction of segment file names
* @pas_id: PAS identifier
* @mem_region: allocated memory region to load firmware into
* @mem_phys: physical address of allocated memory region
@@ -450,41 +463,20 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw,
* Returns 0 on success, negative errno otherwise.
*/
int qcom_mdt_load(struct device *dev, const struct firmware *fw,
const char *firmware, int pas_id, void *mem_region,
const char *fw_name, int pas_id, void *mem_region,
phys_addr_t mem_phys, size_t mem_size,
phys_addr_t *reloc_base)
{
int ret;
ret = qcom_mdt_pas_init(dev, fw, firmware, pas_id, mem_phys, NULL);
ret = qcom_mdt_pas_init(dev, fw, fw_name, pas_id, mem_phys, NULL);
if (ret)
return ret;
return __qcom_mdt_load(dev, fw, firmware, mem_region, mem_phys,
mem_size, reloc_base);
return qcom_mdt_load_no_init(dev, fw, fw_name, mem_region, mem_phys,
mem_size, reloc_base);
}
EXPORT_SYMBOL_GPL(qcom_mdt_load);
/**
* qcom_mdt_load_no_init() - load the firmware which header is loaded as fw
* @dev: device handle to associate resources with
* @fw: firmware object for the mdt file
* @firmware: name of the firmware, for construction of segment file names
* @mem_region: allocated memory region to load firmware into
* @mem_phys: physical address of allocated memory region
* @mem_size: size of the allocated memory region
* @reloc_base: adjusted physical address after relocation
*
* Returns 0 on success, negative errno otherwise.
*/
int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
const char *firmware, void *mem_region, phys_addr_t mem_phys,
size_t mem_size, phys_addr_t *reloc_base)
{
return __qcom_mdt_load(dev, fw, firmware, mem_region, mem_phys,
mem_size, reloc_base);
}
EXPORT_SYMBOL_GPL(qcom_mdt_load_no_init);
MODULE_DESCRIPTION("Firmware parser for Qualcomm MDT format");
MODULE_LICENSE("GPL v2");

2
drivers/soc/qcom/ocmem.c
View File

@@ -202,9 +202,9 @@ struct ocmem *of_get_ocmem(struct device *dev)
}
ocmem = platform_get_drvdata(pdev);
put_device(&pdev->dev);
if (!ocmem) {
dev_err(dev, "Cannot get ocmem\n");
put_device(&pdev->dev);
return ERR_PTR(-ENODEV);
}
return ocmem;

9
drivers/soc/qcom/pmic_glink.c
View File

@@ -39,6 +39,7 @@ struct pmic_glink {
struct mutex state_lock;
unsigned int client_state;
unsigned int pdr_state;
bool pdr_available;
/* serializing clients list updates */
spinlock_t client_lock;
@@ -246,9 +247,12 @@ static int pmic_glink_rpmsg_probe(struct rpmsg_device *rpdev)
return dev_err_probe(&rpdev->dev, -ENODEV, "no pmic_glink device to attach to\n");
dev_set_drvdata(&rpdev->dev, pg);
pg->pdr_available = rpdev->id.driver_data;
guard(mutex)(&pg->state_lock);
pg->ept = rpdev->ept;
if (!pg->pdr_available)
pg->pdr_state = SERVREG_SERVICE_STATE_UP;
pmic_glink_state_notify_clients(pg);
return 0;
@@ -265,11 +269,14 @@ static void pmic_glink_rpmsg_remove(struct rpmsg_device *rpdev)
guard(mutex)(&pg->state_lock);
pg->ept = NULL;
if (!pg->pdr_available)
pg->pdr_state = SERVREG_SERVICE_STATE_DOWN;
pmic_glink_state_notify_clients(pg);
}
static const struct rpmsg_device_id pmic_glink_rpmsg_id_match[] = {
{ "PMIC_RTR_ADSP_APPS" },
{.name = "PMIC_RTR_ADSP_APPS", .driver_data = true },
{.name = "PMIC_RTR_SOCCP_APPS", .driver_data = false },
{}
};

2
drivers/soc/qcom/qcom-pbs.c
View File

@@ -173,6 +173,8 @@ struct pbs_dev *get_pbs_client_device(struct device *dev)
return ERR_PTR(-EINVAL);
}
platform_device_put(pdev);
return pbs;
}
EXPORT_SYMBOL_GPL(get_pbs_client_device);

8
drivers/soc/qcom/qcom_gsbi.c
View File

@@ -212,13 +212,6 @@ static int gsbi_probe(struct platform_device *pdev)
return of_platform_populate(node, NULL, NULL, &pdev->dev);
}
static void gsbi_remove(struct platform_device *pdev)
{
struct gsbi_info *gsbi = platform_get_drvdata(pdev);
clk_disable_unprepare(gsbi->hclk);
}
static const struct of_device_id gsbi_dt_match[] = {
{ .compatible = "qcom,gsbi-v1.0.0", },
{ },
@@ -232,7 +225,6 @@ static struct platform_driver gsbi_driver = {
.of_match_table = gsbi_dt_match,
},
.probe = gsbi_probe,
.remove = gsbi_remove,
};
module_platform_driver(gsbi_driver);

10
drivers/soc/qcom/qcom_pd_mapper.c
View File

@@ -360,6 +360,15 @@ static const struct qcom_pdm_domain_data mpss_wlan_pd = {
},
};
static const struct qcom_pdm_domain_data *kaanapali_domains[] = {
&adsp_audio_pd,
&adsp_root_pd,
&adsp_sensor_pd,
&cdsp_root_pd,
&mpss_root_pd_gps,
NULL,
};
static const struct qcom_pdm_domain_data *msm8996_domains[] = {
&msm8996_adsp_audio_pd,
&msm8996_adsp_root_pd,
@@ -552,6 +561,7 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = {
{ .compatible = "qcom,apq8074", .data = NULL, },
{ .compatible = "qcom,apq8084", .data = NULL, },
{ .compatible = "qcom,apq8096", .data = msm8996_domains, },
{ .compatible = "qcom,kaanapali", .data = kaanapali_domains, },
{ .compatible = "qcom,msm8226", .data = NULL, },
{ .compatible = "qcom,msm8909", .data = NULL, },
{ .compatible = "qcom,msm8916", .data = NULL, },

33
drivers/soc/qcom/smem.c
View File

@@ -353,8 +353,12 @@ static void *cached_entry_to_item(struct smem_private_entry *e)
return p - le32_to_cpu(e->size);
}
/* Pointer to the one and only smem handle */
static struct qcom_smem *__smem;
/*
* Pointer to the one and only smem handle.
* Init to -EPROBE_DEFER to signal SMEM still has to be probed.
* Can be set to -ENODEV if SMEM is not initialized by SBL.
*/
static struct qcom_smem *__smem = INIT_ERR_PTR(-EPROBE_DEFER);
/* Timeout (ms) for the trylock of remote spinlocks */
#define HWSPINLOCK_TIMEOUT 1000
@@ -508,8 +512,8 @@ int qcom_smem_alloc(unsigned host, unsigned item, size_t size)
unsigned long flags;
int ret;
if (!__smem)
return -EPROBE_DEFER;
if (IS_ERR(__smem))
return PTR_ERR(__smem);
if (item < SMEM_ITEM_LAST_FIXED) {
dev_err(__smem->dev,
@@ -517,7 +521,7 @@ int qcom_smem_alloc(unsigned host, unsigned item, size_t size)
return -EINVAL;
}
if (WARN_ON(item >= __smem->item_count))
if (item >= __smem->item_count)
return -EINVAL;
ret = hwspin_lock_timeout_irqsave(__smem->hwlock,
@@ -685,12 +689,12 @@ invalid_canary:
void *qcom_smem_get(unsigned host, unsigned item, size_t *size)
{
struct smem_partition *part;
void *ptr = ERR_PTR(-EPROBE_DEFER);
void *ptr;
if (!__smem)
return ptr;
if (IS_ERR(__smem))
return __smem;
if (WARN_ON(item >= __smem->item_count))
if (item >= __smem->item_count)
return ERR_PTR(-EINVAL);
if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) {
@@ -723,8 +727,8 @@ int qcom_smem_get_free_space(unsigned host)
struct smem_header *header;
unsigned ret;
if (!__smem)
return -EPROBE_DEFER;
if (IS_ERR(__smem))
return PTR_ERR(__smem);
if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) {
part = &__smem->partitions[host];
@@ -1181,8 +1185,8 @@ static int qcom_smem_probe(struct platform_device *pdev)
header = smem->regions[0].virt_base;
if (le32_to_cpu(header->initialized) != 1 ||
le32_to_cpu(header->reserved)) {
dev_err(&pdev->dev, "SMEM is not initialized by SBL\n");
return -EINVAL;
__smem = ERR_PTR(-ENODEV);
return dev_err_probe(&pdev->dev, PTR_ERR(__smem), "SMEM is not initialized by SBL\n");
}
hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
@@ -1190,7 +1194,7 @@ static int qcom_smem_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, hwlock_id,
"failed to retrieve hwlock\n");
smem->hwlock = hwspin_lock_request_specific(hwlock_id);
smem->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, hwlock_id);
if (!smem->hwlock)
return -ENXIO;
@@ -1243,7 +1247,6 @@ static void qcom_smem_remove(struct platform_device *pdev)
{
platform_device_unregister(__smem->socinfo);
hwspin_lock_free(__smem->hwlock);
__smem = NULL;
}

106
drivers/soc/qcom/socinfo.c
View File

@@ -37,7 +37,13 @@
*/
#define SMEM_IMAGE_TABLE_BOOT_INDEX 0
#define SMEM_IMAGE_TABLE_TZ_INDEX 1
#define SMEM_IMAGE_TABLE_TZSECAPP_INDEX 2
#define SMEM_IMAGE_TABLE_RPM_INDEX 3
#define SMEM_IMAGE_TABLE_SDI_INDEX 4
#define SMEM_IMAGE_TABLE_HYP_INDEX 5
#define SMEM_IMAGE_TABLE_ADSP1_INDEX 6
#define SMEM_IMAGE_TABLE_ADSP2_INDEX 7
#define SMEM_IMAGE_TABLE_CDSP2_INDEX 8
#define SMEM_IMAGE_TABLE_APPSBL_INDEX 9
#define SMEM_IMAGE_TABLE_APPS_INDEX 10
#define SMEM_IMAGE_TABLE_MPSS_INDEX 11
@@ -46,31 +52,77 @@
#define SMEM_IMAGE_TABLE_VIDEO_INDEX 14
#define SMEM_IMAGE_TABLE_DSPS_INDEX 15
#define SMEM_IMAGE_TABLE_CDSP_INDEX 16
#define SMEM_IMAGE_TABLE_NPU_INDEX 17
#define SMEM_IMAGE_TABLE_WPSS_INDEX 18
#define SMEM_IMAGE_TABLE_CDSP1_INDEX 19
#define SMEM_IMAGE_TABLE_GPDSP_INDEX 20
#define SMEM_IMAGE_TABLE_GPDSP1_INDEX 21
#define SMEM_IMAGE_TABLE_SENSORPD_INDEX 22
#define SMEM_IMAGE_TABLE_AUDIOPD_INDEX 23
#define SMEM_IMAGE_TABLE_OEMPD_INDEX 24
#define SMEM_IMAGE_TABLE_CHARGERPD_INDEX 25
#define SMEM_IMAGE_TABLE_OISPD_INDEX 26
#define SMEM_IMAGE_TABLE_SOCCP_INDEX 27
#define SMEM_IMAGE_TABLE_TME_INDEX 28
#define SMEM_IMAGE_TABLE_GEARVM_INDEX 29
#define SMEM_IMAGE_TABLE_UEFI_INDEX 30
#define SMEM_IMAGE_TABLE_CDSP3_INDEX 31
#define SMEM_IMAGE_TABLE_AUDIOPD_ADSP1_INDEX 32
#define SMEM_IMAGE_TABLE_AUDIOPD_ADSP2_INDEX 33
#define SMEM_IMAGE_TABLE_DCP_INDEX 34
#define SMEM_IMAGE_TABLE_OOBS_INDEX 35
#define SMEM_IMAGE_TABLE_OOBNS_INDEX 36
#define SMEM_IMAGE_TABLE_DEVCFG_INDEX 37
#define SMEM_IMAGE_TABLE_BTPD_INDEX 38
#define SMEM_IMAGE_TABLE_QECP_INDEX 39
#define SMEM_IMAGE_VERSION_TABLE 469
#define SMEM_IMAGE_VERSION_TABLE_2 667
/*
* SMEM Image table names
*/
static const char *const socinfo_image_names[] = {
[SMEM_IMAGE_TABLE_ADSP1_INDEX] = "adsp1",
[SMEM_IMAGE_TABLE_ADSP2_INDEX] = "adsp2",
[SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp",
[SMEM_IMAGE_TABLE_APPSBL_INDEX] = "appsbl",
[SMEM_IMAGE_TABLE_APPS_INDEX] = "apps",
[SMEM_IMAGE_TABLE_AUDIOPD_INDEX] = "audiopd",
[SMEM_IMAGE_TABLE_AUDIOPD_ADSP1_INDEX] = "audiopd_adsp1",
[SMEM_IMAGE_TABLE_AUDIOPD_ADSP2_INDEX] = "audiopd_adsp2",
[SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot",
[SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss",
[SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss",
[SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm",
[SMEM_IMAGE_TABLE_TZ_INDEX] = "tz",
[SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video",
[SMEM_IMAGE_TABLE_DSPS_INDEX] = "dsps",
[SMEM_IMAGE_TABLE_CDSP_INDEX] = "cdsp",
[SMEM_IMAGE_TABLE_BTPD_INDEX] = "btpd",
[SMEM_IMAGE_TABLE_CDSP1_INDEX] = "cdsp1",
[SMEM_IMAGE_TABLE_GPDSP_INDEX] = "gpdsp",
[SMEM_IMAGE_TABLE_CDSP2_INDEX] = "cdsp2",
[SMEM_IMAGE_TABLE_CDSP3_INDEX] = "cdsp3",
[SMEM_IMAGE_TABLE_CDSP_INDEX] = "cdsp",
[SMEM_IMAGE_TABLE_CHARGERPD_INDEX] = "chargerpd",
[SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss",
[SMEM_IMAGE_TABLE_DCP_INDEX] = "dcp",
[SMEM_IMAGE_TABLE_DEVCFG_INDEX] = "devcfg",
[SMEM_IMAGE_TABLE_DSPS_INDEX] = "dsps",
[SMEM_IMAGE_TABLE_GEARVM_INDEX] = "gearvm",
[SMEM_IMAGE_TABLE_GPDSP1_INDEX] = "gpdsp1",
[SMEM_IMAGE_TABLE_GPDSP_INDEX] = "gpdsp",
[SMEM_IMAGE_TABLE_HYP_INDEX] = "hyp",
[SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss",
[SMEM_IMAGE_TABLE_NPU_INDEX] = "npu",
[SMEM_IMAGE_TABLE_OEMPD_INDEX] = "oempd",
[SMEM_IMAGE_TABLE_OISPD_INDEX] = "oispd",
[SMEM_IMAGE_TABLE_OOBNS_INDEX] = "oobns",
[SMEM_IMAGE_TABLE_OOBS_INDEX] = "oobs",
[SMEM_IMAGE_TABLE_QECP_INDEX] = "qecp",
[SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm",
[SMEM_IMAGE_TABLE_SDI_INDEX] = "sdi",
[SMEM_IMAGE_TABLE_SENSORPD_INDEX] = "sensorpd",
[SMEM_IMAGE_TABLE_SOCCP_INDEX] = "soccp",
[SMEM_IMAGE_TABLE_TME_INDEX] = "tme",
[SMEM_IMAGE_TABLE_TZ_INDEX] = "tz",
[SMEM_IMAGE_TABLE_TZSECAPP_INDEX] = "tzsecapp",
[SMEM_IMAGE_TABLE_UEFI_INDEX] = "uefi",
[SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video",
[SMEM_IMAGE_TABLE_WPSS_INDEX] = "wpss",
};
static const char *const pmic_models[] = {
@@ -161,6 +213,7 @@ struct socinfo_params {
u32 num_func_clusters;
u32 boot_cluster;
u32 boot_core;
u32 raw_package_type;
};
struct smem_image_version {
@@ -415,6 +468,7 @@ static const struct soc_id soc_id[] = {
{ qcom_board_id(SC7280) },
{ qcom_board_id(SC7180P) },
{ qcom_board_id(QCM6490) },
{ qcom_board_id(QCS6490) },
{ qcom_board_id(SM7325P) },
{ qcom_board_id(IPQ5000) },
{ qcom_board_id(IPQ0509) },
@@ -461,6 +515,7 @@ static const struct soc_id soc_id[] = {
{ qcom_board_id(IPQ5424) },
{ qcom_board_id(QCM6690) },
{ qcom_board_id(QCS6690) },
{ qcom_board_id(SM8850) },
{ qcom_board_id(IPQ5404) },
{ qcom_board_id(QCS9100) },
{ qcom_board_id(QCS8300) },
@@ -609,7 +664,7 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
struct smem_image_version *versions;
struct dentry *dentry;
size_t size;
int i;
int i, j;
unsigned int num_pmics;
unsigned int pmic_array_offset;
@@ -621,6 +676,14 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
&qcom_socinfo->info.fmt);
switch (qcom_socinfo->info.fmt) {
case SOCINFO_VERSION(0, 23):
case SOCINFO_VERSION(0, 22):
case SOCINFO_VERSION(0, 21):
case SOCINFO_VERSION(0, 20):
qcom_socinfo->info.raw_package_type = __le32_to_cpu(info->raw_package_type);
debugfs_create_u32("raw_package_type", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.raw_package_type);
fallthrough;
case SOCINFO_VERSION(0, 19):
qcom_socinfo->info.num_func_clusters = __le32_to_cpu(info->num_func_clusters);
qcom_socinfo->info.boot_cluster = __le32_to_cpu(info->boot_cluster);
@@ -753,20 +816,31 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
break;
}
versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE,
&size);
for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) {
for (i = 0, j = 0; i < ARRAY_SIZE(socinfo_image_names); i++, j++) {
if (!socinfo_image_names[i])
continue;
if (i == 0) {
versions = qcom_smem_get(QCOM_SMEM_HOST_ANY,
SMEM_IMAGE_VERSION_TABLE,
&size);
} else if (i == 32) {
versions = qcom_smem_get(QCOM_SMEM_HOST_ANY,
SMEM_IMAGE_VERSION_TABLE_2,
&size);
if (IS_ERR(versions))
break;
j = 0;
}
dentry = debugfs_create_dir(socinfo_image_names[i],
qcom_socinfo->dbg_root);
debugfs_create_file("name", 0444, dentry, &versions[i],
debugfs_create_file("name", 0444, dentry, &versions[j],
&qcom_image_name_ops);
debugfs_create_file("variant", 0444, dentry, &versions[i],
debugfs_create_file("variant", 0444, dentry, &versions[j],
&qcom_image_variant_ops);
debugfs_create_file("oem", 0444, dentry, &versions[i],
debugfs_create_file("oem", 0444, dentry, &versions[j],
&qcom_image_oem_ops);
}
}

24
drivers/soc/qcom/ubwc_config.c
View File

@@ -16,6 +16,16 @@ static const struct qcom_ubwc_cfg_data no_ubwc_data = {
/* no UBWC, no HBB */
};
static const struct qcom_ubwc_cfg_data kaanapali_data = {
.ubwc_enc_version = UBWC_6_0,
.ubwc_dec_version = UBWC_6_0,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
.highest_bank_bit = 16,
.macrotile_mode = true,
};
static const struct qcom_ubwc_cfg_data msm8937_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_1_0,
@@ -218,11 +228,24 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
.macrotile_mode = true,
};
static const struct qcom_ubwc_cfg_data glymur_data = {
.ubwc_enc_version = UBWC_5_0,
.ubwc_dec_version = UBWC_5_0,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
.macrotile_mode = true,
};
static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
{ .compatible = "qcom,apq8016", .data = &no_ubwc_data },
{ .compatible = "qcom,apq8026", .data = &no_ubwc_data },
{ .compatible = "qcom,apq8074", .data = &no_ubwc_data },
{ .compatible = "qcom,apq8096", .data = &msm8998_data },
{ .compatible = "qcom,kaanapali", .data = &kaanapali_data, },
{ .compatible = "qcom,glymur", .data = &glymur_data},
{ .compatible = "qcom,msm8226", .data = &no_ubwc_data },
{ .compatible = "qcom,msm8916", .data = &no_ubwc_data },
{ .compatible = "qcom,msm8917", .data = &no_ubwc_data },
@@ -237,6 +260,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
{ .compatible = "qcom,msm8998", .data = &msm8998_data },
{ .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
{ .compatible = "qcom,qcm6490", .data = &sc7280_data, },
{ .compatible = "qcom,qcs8300", .data = &sc8280xp_data, },
{ .compatible = "qcom,sa8155p", .data = &sm8150_data, },
{ .compatible = "qcom,sa8540p", .data = &sc8280xp_data, },
{ .compatible = "qcom,sa8775p", .data = &sa8775p_data, },

2
include/dt-bindings/arm/qcom,ids.h
View File

@@ -240,6 +240,7 @@
#define QCOM_ID_SC7280 487
#define QCOM_ID_SC7180P 495
#define QCOM_ID_QCM6490 497
#define QCOM_ID_QCS6490 498
#define QCOM_ID_SM7325P 499
#define QCOM_ID_IPQ5000 503
#define QCOM_ID_IPQ0509 504
@@ -286,6 +287,7 @@
#define QCOM_ID_IPQ5424 651
#define QCOM_ID_QCM6690 657
#define QCOM_ID_QCS6690 658
#define QCOM_ID_SM8850 660
#define QCOM_ID_IPQ5404 671
#define QCOM_ID_QCS9100 667
#define QCOM_ID_QCS8300 674

8
include/linux/err.h
View File

@@ -41,6 +41,14 @@ static inline void * __must_check ERR_PTR(long error)
return (void *) error;
}
/**
* INIT_ERR_PTR - Init a const error pointer.
* @error: A negative error code.
*
* Like ERR_PTR(), but usable to initialize static variables.
*/
#define INIT_ERR_PTR(error) ((void *)(error))
/* Return the pointer in the percpu address space. */
#define ERR_PTR_PCPU(error) ((void __percpu *)(unsigned long)ERR_PTR(error))

15
include/linux/firmware/qcom/qcom_tzmem.h
View File

@@ -17,11 +17,20 @@ struct qcom_tzmem_pool;
* enum qcom_tzmem_policy - Policy for pool growth.
*/
enum qcom_tzmem_policy {
/**< Static pool, never grow above initial size. */
/**
* @QCOM_TZMEM_POLICY_STATIC: Static pool,
* never grow above initial size.
*/
QCOM_TZMEM_POLICY_STATIC = 1,
/**< When out of memory, add increment * current size of memory. */
/**
* @QCOM_TZMEM_POLICY_MULTIPLIER: When out of memory,
* add increment * current size of memory.
*/
QCOM_TZMEM_POLICY_MULTIPLIER,
/**< When out of memory add as much as is needed until max_size. */
/**
* @QCOM_TZMEM_POLICY_ON_DEMAND: When out of memory
* add as much as is needed until max_size.
*/
QCOM_TZMEM_POLICY_ON_DEMAND,
};

7
include/linux/soc/qcom/llcc-qcom.h
View File

@@ -74,7 +74,14 @@
#define LLCC_CAMSRTIP 73
#define LLCC_CAMRTRF 74
#define LLCC_CAMSRTRF 75
#define LLCC_VIDEO_APV 83
#define LLCC_COMPUTE1 87
#define LLCC_CPUSS_OPP 88
#define LLCC_CPUSSMPAM 89
#define LLCC_CAM_IPE_STROV 92
#define LLCC_CAM_OFE_STROV 93
#define LLCC_CPUSS_HEU 94
#define LLCC_MDM_PNG_FIXED 100
/**
* struct llcc_slice_desc - Cache slice descriptor

4
include/linux/soc/qcom/socinfo.h
View File

@@ -82,6 +82,10 @@ struct socinfo {
__le32 num_func_clusters;
__le32 boot_cluster;
__le32 boot_core;
/* Version 20 */
__le32 raw_package_type;
/* Version 21, 22, 23 */
__le32 reserve1[4];
};
/* Internal feature codes */

1
include/linux/soc/qcom/ubwc.h
View File

@@ -52,6 +52,7 @@ struct qcom_ubwc_cfg_data {
#define UBWC_4_0 0x40000000
#define UBWC_4_3 0x40030000
#define UBWC_5_0 0x50000000
#define UBWC_6_0 0x60000000
#if IS_ENABLED(CONFIG_QCOM_UBWC_CONFIG)
const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);