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Merge master.kernel.org:/home/rmk/linux-2.6-arm

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* master.kernel.org:/home/rmk/linux-2.6-arm: (25 commits)
  [ARM] 3648/1: Update struct ucontext layout for coprocessor registers
  [ARM] Add identifying number for non-rt sigframe
  [ARM] Gather common sigframe saving code into setup_sigframe()
  [ARM] Gather common sigframe restoration code into restore_sigframe()
  [ARM] Re-use sigframe within rt_sigframe
  [ARM] Merge sigcontext and sigmask members of sigframe
  [ARM] Replace extramask with a full copy of the sigmask
  [ARM] Remove rt_sigframe puc and pinfo pointers
  [ARM] 3647/1: S3C24XX: add Osiris to the list of simtec pm machines
  [ARM] 3645/1: S3C2412: irq support for external interrupts
  [ARM] 3643/1: S3C2410: Add new usb clocks
  [ARM] 3642/1: S3C24XX: Add machine SMDK2413
  [ARM] 3641/1: S3C2412: Fixup gpio register naming
  [ARM] 3640/1: S3C2412: Use S3C24XX_DCLKCON instead of S3C2410_DCLKCON
  [ARM] 3639/1: S3C2412: serial port support
  [ARM] 3638/1: S3C2412: core clocks
  [ARM] 3637/1: S3C24XX: Add mpll clock, and set as fclk parent
  [ARM] 3636/1: S3C2412: Add selection of CPU_ARM926
  [ARM] 3635/1: S3C24XX: Add S3C2412 core cpu support
  [ARM] 3633/1: S3C24XX: s3c2410 gpio bugfix - wrong pin nos
  ...
This commit is contained in:
Linus Torvalds
2006-06-24 17:48:14 -07:00
parent 83626b0127 c089785655
commit dfd8317d33
49 changed files with 1879 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
include/asm-arm/arch-aaec2000/io.h
View File

@@ -16,6 +16,5 @@
*/
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

1
include/asm-arm/arch-clps711x/io.h
View File

@@ -26,7 +26,6 @@
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
/*
* We don't support ins[lb]/outs[lb]. Make them fault.

8
include/asm-arm/arch-ebsa285/io.h
View File

@@ -24,7 +24,6 @@
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#if 1
#define __mem_pci(a) (a)
#define __mem_isa(a) ((a) + PCIMEM_BASE)
#else
static inline void __iomem *___mem_pci(void __iomem *p)
@@ -34,14 +33,7 @@ static inline void __iomem *___mem_pci(void __iomem *p)
return p;
}
static inline void __iomem *___mem_isa(void __iomem *p)
{
unsigned long a = (unsigned long)p;
BUG_ON(a >= 16*1048576);
return p + PCIMEM_BASE;
}
#define __mem_pci(a) ___mem_pci(a)
#define __mem_isa(a) ___mem_isa(a)
#endif
#endif

2
include/asm-arm/arch-ep93xx/ep93xx-regs.h
View File

@@ -115,6 +115,8 @@
#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24)
#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80)
#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)

1
include/asm-arm/arch-ep93xx/platform.h
View File

@@ -8,6 +8,7 @@ void ep93xx_map_io(void);
void ep93xx_init_irq(void);
void ep93xx_init_time(unsigned long);
void ep93xx_init_devices(void);
void ep93xx_clock_init(void);
extern struct sys_timer ep93xx_timer;

1
include/asm-arm/arch-integrator/io.h
View File

@@ -32,6 +32,5 @@
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
#endif

1
include/asm-arm/arch-iop3xx/io.h
View File

@@ -17,6 +17,5 @@
#define __io(p) ((void __iomem *)(p))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

1
include/asm-arm/arch-l7200/io.h
View File

@@ -19,7 +19,6 @@
*/
#define __io_pci(a) ((void __iomem *)(PCIO_BASE + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#define __ioaddr(p) __io_pci(p)

1
include/asm-arm/arch-lh7a40x/io.h
View File

@@ -18,6 +18,5 @@
/* No ISA or PCI bus on this machine. */
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif /* __ASM_ARCH_IO_H */

1
include/asm-arm/arch-netx/io.h
View File

@@ -24,6 +24,5 @@
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

1
include/asm-arm/arch-omap/io.h
View File

@@ -44,7 +44,6 @@
*/
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
/*
* ----------------------------------------------------------------------------

1
include/asm-arm/arch-pxa/io.h
View File

@@ -16,6 +16,5 @@
*/
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

1
include/asm-arm/arch-realview/io.h
View File

@@ -29,6 +29,5 @@ static inline void __iomem *__io(unsigned long addr)
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

10
include/asm-arm/arch-s3c2410/debug-macro.S
View File

@@ -33,7 +33,7 @@
.endm
.macro senduart,rd,rx
str \rd, [\rx, # S3C2410_UTXH ]
strb \rd, [\rx, # S3C2410_UTXH ]
.endm
.macro busyuart, rd, rx
@@ -42,6 +42,12 @@
beq 1001f @
@ FIFO enabled...
1003:
@ check for arm920 vs arm926. currently assume all arm926
@ devices have an 64 byte FIFO identical to the s3c2440
mrc p15, 0, \rd, c0, c0
and \rd, \rd, #0xff0
teq \rd, #0x260
beq 1004f
mrc p15, 0, \rd, c1, c0
tst \rd, #1
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -50,7 +56,7 @@
ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
and \rd, \rd, #0x00ff0000
teq \rd, #0x00440000 @ is it 2440?
1004:
ldr \rd, [ \rx, # S3C2410_UFSTAT ]
moveq \rd, \rd, lsr #SHIFT_2440TXF
tst \rd, #S3C2410_UFSTAT_TXFULL

30
include/asm-arm/arch-s3c2410/entry-macro.S
View File

@@ -18,8 +18,6 @@
#define INTPND (0x10)
#define INTOFFSET (0x14)
#define EXTINTPEND (0xa8)
#define EXTINTMASK (0xa4)
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
@@ -28,37 +26,23 @@
mov \base, #S3C24XX_VA_IRQ
ldr \irqstat, [ \base, #INTPND]
bics \irqnr, \irqstat, #3<<4 @@ only an GPIO IRQ
beq 2000f
@@ try the interrupt offset register, since it is there
ldr \irqstat, [ \base, #INTPND ]
teq \irqstat, #0
beq 1002f
ldr \irqnr, [ \base, #INTOFFSET ]
mov \tmp, #1
tst \irqstat, \tmp, lsl \irqnr
addne \irqnr, \irqnr, #IRQ_EINT0
bne 1001f
@@ the number specified is not a valid irq, so try
@@ and work it out for ourselves
mov \irqnr, #IRQ_EINT0 @@ start here
b 3000f
2000:
@@ load the GPIO interrupt register, and check it
add \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
ldr \irqstat, [ \tmp, # EXTINTPEND ]
ldr \irqnr, [ \tmp, # EXTINTMASK ]
bics \irqstat, \irqstat, \irqnr
beq 1001f
mov \irqnr, #(IRQ_EINT4 - 4)
mov \irqnr, #0 @@ start here
@@ work out which irq (if any) we got
3000:
movs \tmp, \irqstat, lsl#16
addeq \irqnr, \irqnr, #16
moveq \irqstat, \irqstat, lsr#16
@@ -75,9 +59,9 @@
addeq \irqnr, \irqnr, #1
@@ we have the value
movs \irqnr, \irqnr
1001:
adds \irqnr, \irqnr, #IRQ_EINT0
1002:
@@ exit here, Z flag unset if IRQ
.endm

16
include/asm-arm/arch-s3c2410/map.h
View File

@@ -236,4 +236,20 @@
#define S3C24XX_PA_SPI S3C2410_PA_SPI
#endif
/* deal with the registers that move under the 2412/2413 */
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#ifndef __ASSEMBLY__
extern void __iomem *s3c24xx_va_gpio2;
#endif
#ifdef CONFIG_CPU_S3C2412_ONLY
#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
#else
#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
#endif
#else
#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
#endif
#endif /* __ASM_ARCH_MAP_H */

63
include/asm-arm/arch-s3c2410/regs-clock.h
View File

@@ -1,6 +1,6 @@
/* linux/include/asm/arch-s3c2410/regs-clock.h
*
* Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
* Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
@@ -140,5 +140,66 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
#define S3C2412_PLLCON_OFF (1<<20)
#define S3C2412_CLKDIVN_PDIVN (1<<2)
#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
#define S3C2421_CLKDIVN_ARMDIVN (1<<3)
#define S3C2412_CLKDIVN_USB48DIV (1<<6)
#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
#define S3C2412_CLKCON_WDT (1<<28)
#define S3C2412_CLKCON_SPI (1<<27)
#define S3C2412_CLKCON_IIS (1<<26)
#define S3C2412_CLKCON_IIC (1<<25)
#define S3C2412_CLKCON_ADC (1<<24)
#define S3C2412_CLKCON_RTC (1<<23)
#define S3C2412_CLKCON_GPIO (1<<22)
#define S3C2412_CLKCON_UART2 (1<<21)
#define S3C2412_CLKCON_UART1 (1<<20)
#define S3C2412_CLKCON_UART0 (1<<19)
#define S3C2412_CLKCON_SDI (1<<18)
#define S3C2412_CLKCON_PWMT (1<<17)
#define S3C2412_CLKCON_USBD (1<<16)
#define S3C2412_CLKCON_CAMCLK (1<<15)
#define S3C2412_CLKCON_UARTCLK (1<<14)
/* missing 13 */
#define S3C2412_CLKCON_USB_HOST48 (1<<12)
#define S3C2412_CLKCON_USB_DEV48 (1<<11)
#define S3C2412_CLKCON_HCLKdiv2 (1<<10)
#define S3C2412_CLKCON_HCLKx2 (1<<9)
#define S3C2412_CLKCON_SDRAM (1<<8)
/* missing 7 */
#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
#define S3C2412_CLKCON_DMA3 (1<<3)
#define S3C2412_CLKCON_DMA2 (1<<2)
#define S3C2412_CLKCON_DMA1 (1<<1)
#define S3C2412_CLKCON_DMA0 (1<<0)
/* clock sourec controls */
#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
#endif /* __ASM_ARM_REGS_CLOCK */

3
include/asm-arm/arch-s3c2410/regs-dsc.h
View File

@@ -23,6 +23,9 @@
#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
#define S3C2440_SELECT_DSC0 (0)
#define S3C2440_SELECT_DSC1 (1<<31)

63
include/asm-arm/arch-s3c2410/regs-gpio.h
View File

@@ -45,7 +45,7 @@
#define S3C24XX_MISCCR S3C2400_MISCCR
#else
#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
#define S3C24XX_MISCCR S3C2410_MISCCR
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
#endif /* CONFIG_CPU_S3C2400 */
@@ -73,9 +73,15 @@
#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
/* configure GPIO ports A..G */
/* register address for the GPIO registers.
* S3C24XX_GPIOREG2 is for the second set of registers in the
* GPIO which move between s3c2410 and s3c2412 type systems */
#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
/* configure GPIO ports A..G */
/* port A - S3C2410: 22bits, zero in bit X makes pin X output
* S3C2400: 18bits, zero in bit X makes pin X output
@@ -953,11 +959,18 @@
#define S3C2410_GPH10_OUTP (0x01 << 20)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
/* The S3C2412 and S3C2413 move the GPJ register set to after
* GPH, which means all registers after 0x80 are now offset by 0x10
* for the 2412/2413 from the 2410/2440/2442
*/
/* miscellaneous control */
#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
/* see clock.h for dclk definitions */
/* pullup control on databus */
@@ -985,6 +998,8 @@
#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
#define S3C2410_MISCCR_CLK0_MASK (7<<4)
#define S3C2412_MISCCR_CLK0_RTC (2<<4)
#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
@@ -993,6 +1008,8 @@
#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
#define S3C2410_MISCCR_CLK1_MASK (7<<8)
#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
@@ -1000,7 +1017,7 @@
#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
#define S3C2410_MISCCR_nEN_SCLKE (1<<19)
#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
#define S3C2410_MISCCR_SDSLEEP (7<<17)
/* external interrupt control... */
@@ -1017,6 +1034,10 @@
#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
/* values for S3C2410_EXTINT0/1/2 */
#define S3C2410_EXTINT_LOWLEV (0x00)
#define S3C2410_EXTINT_HILEV (0x01)
@@ -1030,6 +1051,11 @@
#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
/* values for interrupt filtering */
#define S3C2410_EINTFLT_PCLK (0x00)
#define S3C2410_EINTFLT_EXTCLK (1<<7)
@@ -1039,6 +1065,7 @@
/* GSTATUS have miscellaneous information in them
*
* These move between s3c2410 and s3c2412 style systems.
*/
#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
@@ -1047,6 +1074,18 @@
#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
#define S3C2410_GSTATUS0_nWAIT (1<<3)
#define S3C2410_GSTATUS0_NCON (1<<2)
#define S3C2410_GSTATUS0_RnB (1<<1)
@@ -1054,6 +1093,7 @@
#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
#define S3C2410_GSTATUS1_2410 (0x32410000)
#define S3C2410_GSTATUS1_2412 (0x32412001)
#define S3C2410_GSTATUS1_2440 (0x32440000)
#define S3C2410_GSTATUS1_2442 (0x32440aaa)
@@ -1077,5 +1117,22 @@
#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
/* 2412/2413 sleep configuration registers */
#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
#define S3C2412_GPESLPCON S3C2410_GPIOREG(0x4C)
#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
/* definitions for each pin bit */
#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
#define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2))
#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
#define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2))
#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
#endif /* __ASM_ARCH_REGS_GPIO_H */

5
include/asm-arm/arch-s3c2410/regs-gpioj.h
View File

@@ -32,6 +32,11 @@
#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
#define S3C2440_GPJ0_INP (0x00 << 0)
#define S3C2440_GPJ0_OUTP (0x01 << 0)

6
include/asm-arm/arch-s3c2410/regs-irq.h
View File

@@ -23,6 +23,7 @@
#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
@@ -40,5 +41,10 @@
#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
#endif /* ___ASM_ARCH_REGS_IRQ_H */

15
include/asm-arm/arch-s3c2410/regs-serial.h
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@@ -82,6 +82,12 @@
#define S3C2440_UCON2_DIVMASK (7 << 12)
#define S3C2440_UCON_DIVSHIFT (12)
#define S3C2412_UCON_CLKMASK (3<<10)
#define S3C2412_UCON_UCLK (1<<10)
#define S3C2412_UCON_USYSCLK (3<<10)
#define S3C2412_UCON_PCLK (0<<10)
#define S3C2412_UCON_PCLK2 (2<<10)
#define S3C2410_UCON_UCLK (1<<10)
#define S3C2410_UCON_SBREAK (1<<4)
@@ -124,6 +130,15 @@
#define S3C2410_UMCOM_AFC (1<<4)
#define S3C2410_UMCOM_RTS_LOW (1<<0)
#define S3C2412_UMCON_AFC_63 (0<<5)
#define S3C2412_UMCON_AFC_56 (1<<5)
#define S3C2412_UMCON_AFC_48 (2<<5)
#define S3C2412_UMCON_AFC_40 (3<<5)
#define S3C2412_UMCON_AFC_32 (4<<5)
#define S3C2412_UMCON_AFC_24 (5<<5)
#define S3C2412_UMCON_AFC_16 (6<<5)
#define S3C2412_UMCON_AFC_8 (7<<5)
#define S3C2410_UFSTAT_TXFULL (1<<9)
#define S3C2410_UFSTAT_RXFULL (1<<8)
#define S3C2410_UFSTAT_TXMASK (15<<4)

1
include/asm-arm/arch-sa1100/io.h
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@@ -22,6 +22,5 @@ static inline void __iomem *__io(unsigned long addr)
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

1
include/asm-arm/arch-versatile/io.h
View File

@@ -28,6 +28,5 @@ static inline void __iomem *__io(unsigned long addr)
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

79
include/asm-arm/ucontext.h
View File

@@ -1,12 +1,89 @@
#ifndef _ASMARM_UCONTEXT_H
#define _ASMARM_UCONTEXT_H
#include <asm/fpstate.h>
/*
* struct sigcontext only has room for the basic registers, but struct
* ucontext now has room for all registers which need to be saved and
* restored. Coprocessor registers are stored in uc_regspace. Each
* coprocessor's saved state should start with a documented 32-bit magic
* number, followed by a 32-bit word giving the coproccesor's saved size.
* uc_regspace may be expanded if necessary, although this takes some
* coordination with glibc.
*/
struct ucontext {
unsigned long uc_flags;
struct ucontext *uc_link;
stack_t uc_stack;
struct sigcontext uc_mcontext;
sigset_t uc_sigmask; /* mask last for extensibility */
sigset_t uc_sigmask;
/* Allow for uc_sigmask growth. Glibc uses a 1024-bit sigset_t. */
int __unused[32 - (sizeof (sigset_t) / sizeof (int))];
/* Last for extensibility. Eight byte aligned because some
coprocessors require eight byte alignment. */
unsigned long uc_regspace[128] __attribute__((__aligned__(8)));
};
#ifdef __KERNEL__
/*
* Coprocessor save state. The magic values and specific
* coprocessor's layouts are part of the userspace ABI. Each one of
* these should be a multiple of eight bytes and aligned to eight
* bytes, to prevent unpredictable padding in the signal frame.
*/
#ifdef CONFIG_IWMMXT
/* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */
#define IWMMXT_MAGIC 0x12ef842a
#define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8)
struct iwmmxt_sigframe {
unsigned long magic;
unsigned long size;
struct iwmmxt_struct storage;
} __attribute__((__aligned__(8)));
#endif /* CONFIG_IWMMXT */
#ifdef CONFIG_VFP
#if __LINUX_ARM_ARCH__ < 6
/* For ARM pre-v6, we use fstmiax and fldmiax. This adds one extra
* word after the registers, and a word of padding at the end for
* alignment. */
#define VFP_MAGIC 0x56465001
#define VFP_STORAGE_SIZE 152
#else
#define VFP_MAGIC 0x56465002
#define VFP_STORAGE_SIZE 144
#endif
struct vfp_sigframe
{
unsigned long magic;
unsigned long size;
union vfp_state storage;
};
#endif /* CONFIG_VFP */
/*
* Auxiliary signal frame. This saves stuff like FP state.
* The layout of this structure is not part of the user ABI,
* because the config options aren't. uc_regspace is really
* one of these.
*/
struct aux_sigframe {
#ifdef CONFIG_IWMMXT
struct iwmmxt_sigframe iwmmxt;
#endif
#if 0 && defined CONFIG_VFP /* Not yet saved. */
struct vfp_sigframe vfp;
#endif
/* Something that isn't a valid magic number for any coprocessor. */
unsigned long end_magic;
} __attribute__((__aligned__(8)));
#endif
#endif /* !_ASMARM_UCONTEXT_H */

3
include/linux/serial_core.h
View File

@@ -130,6 +130,9 @@
/* SUN4V Hypervisor Console */
#define PORT_SUNHV 72
#define PORT_S3C2412 73
#ifdef __KERNEL__
#include <linux/compiler.h>