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Merge tag 'renesas-drivers-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers

Browse Source 
Renesas driver updates for v6.19 (take two)

  - Fix accessing forbidden registers from regmap debugfs on RZ/G3E,
    RZ/G3S, RZ/V2H, and RZ/V2N.

* tag 'renesas-drivers-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config
  soc: renesas: r9a09g056-sys: Populate max_register

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-25 10:23:26 +01:00
parent babf4c8841 c432180a7d
commit 9b26d16d79
6 changed files with 324 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

69
drivers/soc/renesas/r9a08g045-sysc.c
View File

@@ -6,10 +6,29 @@
*/ */
#include <linux/bits.h> #include <linux/bits.h>
#include <linux/device.h>
#include <linux/init.h> #include <linux/init.h>
#include "rz-sysc.h" #include "rz-sysc.h"
#define SYS_XSPI_MAP_STAADD_CS0 0x348
#define SYS_XSPI_MAP_ENDADD_CS0 0x34c
#define SYS_XSPI_MAP_STAADD_CS1 0x350
#define SYS_XSPI_MAP_ENDADD_CS1 0x354
#define SYS_GETH0_CFG 0x380
#define SYS_GETH1_CFG 0x390
#define SYS_PCIE_CFG 0x3a0
#define SYS_PCIE_MON 0x3a4
#define SYS_PCIE_ERR_MON 0x3ac
#define SYS_PCIE_PHY 0x3b4
#define SYS_I2C0_CFG 0x400
#define SYS_I2C1_CFG 0x410
#define SYS_I2C2_CFG 0x420
#define SYS_I2C3_CFG 0x430
#define SYS_I3C_CFG 0x440
#define SYS_USB_PWRRDY 0xd70
#define SYS_PCIE_RST_RSM_B 0xd74
static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = { static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = {
.family = "RZ/G3S", .family = "RZ/G3S",
.id = 0x85e0447, .id = 0x85e0447,
@@ -18,7 +37,57 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc
.specific_id_mask = GENMASK(27, 0), .specific_id_mask = GENMASK(27, 0),
}; };
static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_XSPI_MAP_STAADD_CS0:
case SYS_XSPI_MAP_ENDADD_CS0:
case SYS_XSPI_MAP_STAADD_CS1:
case SYS_XSPI_MAP_ENDADD_CS1:
case SYS_GETH0_CFG:
case SYS_GETH1_CFG:
case SYS_PCIE_CFG:
case SYS_PCIE_MON:
case SYS_PCIE_ERR_MON:
case SYS_PCIE_PHY:
case SYS_I2C0_CFG:
case SYS_I2C1_CFG:
case SYS_I2C2_CFG:
case SYS_I2C3_CFG:
case SYS_I3C_CFG:
case SYS_USB_PWRRDY:
case SYS_PCIE_RST_RSM_B:
return true;
default:
return false;
}
}
static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_XSPI_MAP_STAADD_CS0:
case SYS_XSPI_MAP_ENDADD_CS0:
case SYS_XSPI_MAP_STAADD_CS1:
case SYS_XSPI_MAP_ENDADD_CS1:
case SYS_PCIE_CFG:
case SYS_PCIE_PHY:
case SYS_I2C0_CFG:
case SYS_I2C1_CFG:
case SYS_I2C2_CFG:
case SYS_I2C3_CFG:
case SYS_I3C_CFG:
case SYS_USB_PWRRDY:
case SYS_PCIE_RST_RSM_B:
return true;
default:
return false;
}
}
const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = { const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = {
.soc_id_init_data = &rzg3s_sysc_soc_id_init_data, .soc_id_init_data = &rzg3s_sysc_soc_id_init_data,
.readable_reg = rzg3s_regmap_readable_reg,
.writeable_reg = rzg3s_regmap_writeable_reg,
.max_register = 0xe20, .max_register = 0xe20,
}; };

79
drivers/soc/renesas/r9a09g047-sys.c
View File

@@ -29,6 +29,27 @@
#define SYS_LSI_PRR_CA55_DIS BIT(8) #define SYS_LSI_PRR_CA55_DIS BIT(8)
#define SYS_LSI_PRR_NPU_DIS BIT(1) #define SYS_LSI_PRR_NPU_DIS BIT(1)
#define SYS_LSI_OTPTSU1TRMVAL0 0x330
#define SYS_LSI_OTPTSU1TRMVAL1 0x334
#define SYS_SPI_STAADDCS0 0x900
#define SYS_SPI_ENDADDCS0 0x904
#define SYS_SPI_STAADDCS1 0x908
#define SYS_SPI_ENDADDCS1 0x90c
#define SYS_VSP_CLK 0xe00
#define SYS_GBETH0_CFG 0xf00
#define SYS_GBETH1_CFG 0xf04
#define SYS_PCIE_INTX_CH0 0x1000
#define SYS_PCIE_MSI1_CH0 0x1004
#define SYS_PCIE_MSI2_CH0 0x1008
#define SYS_PCIE_MSI3_CH0 0x100c
#define SYS_PCIE_MSI4_CH0 0x1010
#define SYS_PCIE_MSI5_CH0 0x1014
#define SYS_PCIE_PME_CH0 0x1018
#define SYS_PCIE_ACK_CH0 0x101c
#define SYS_PCIE_MISC_CH0 0x1020
#define SYS_PCIE_MODE_CH0 0x1024
#define SYS_ADC_CFG 0x1600
static void rzg3e_sys_print_id(struct device *dev, static void rzg3e_sys_print_id(struct device *dev,
void __iomem *sysc_base, void __iomem *sysc_base,
struct soc_device_attribute *soc_dev_attr) struct soc_device_attribute *soc_dev_attr)
@@ -62,7 +83,65 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initco
.print_id = rzg3e_sys_print_id, .print_id = rzg3e_sys_print_id,
}; };
static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_LSI_OTPTSU1TRMVAL0:
case SYS_LSI_OTPTSU1TRMVAL1:
case SYS_SPI_STAADDCS0:
case SYS_SPI_ENDADDCS0:
case SYS_SPI_STAADDCS1:
case SYS_SPI_ENDADDCS1:
case SYS_VSP_CLK:
case SYS_GBETH0_CFG:
case SYS_GBETH1_CFG:
case SYS_PCIE_INTX_CH0:
case SYS_PCIE_MSI1_CH0:
case SYS_PCIE_MSI2_CH0:
case SYS_PCIE_MSI3_CH0:
case SYS_PCIE_MSI4_CH0:
case SYS_PCIE_MSI5_CH0:
case SYS_PCIE_PME_CH0:
case SYS_PCIE_ACK_CH0:
case SYS_PCIE_MISC_CH0:
case SYS_PCIE_MODE_CH0:
case SYS_ADC_CFG:
return true;
default:
return false;
}
}
static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_SPI_STAADDCS0:
case SYS_SPI_ENDADDCS0:
case SYS_SPI_STAADDCS1:
case SYS_SPI_ENDADDCS1:
case SYS_VSP_CLK:
case SYS_GBETH0_CFG:
case SYS_GBETH1_CFG:
case SYS_PCIE_INTX_CH0:
case SYS_PCIE_MSI1_CH0:
case SYS_PCIE_MSI2_CH0:
case SYS_PCIE_MSI3_CH0:
case SYS_PCIE_MSI4_CH0:
case SYS_PCIE_MSI5_CH0:
case SYS_PCIE_PME_CH0:
case SYS_PCIE_ACK_CH0:
case SYS_PCIE_MISC_CH0:
case SYS_PCIE_MODE_CH0:
case SYS_ADC_CFG:
return true;
default:
return false;
}
}
const struct rz_sysc_init_data rzg3e_sys_init_data = { const struct rz_sysc_init_data rzg3e_sys_init_data = {
.soc_id_init_data = &rzg3e_sys_soc_id_init_data, .soc_id_init_data = &rzg3e_sys_soc_id_init_data,
.readable_reg = rzg3e_regmap_readable_reg,
.writeable_reg = rzg3e_regmap_writeable_reg,
.max_register = 0x170c, .max_register = 0x170c,
}; };

69
drivers/soc/renesas/r9a09g056-sys.c
View File

@@ -34,6 +34,24 @@
#define SYS_RZV2N_FEATURE_C55 BIT(1) #define SYS_RZV2N_FEATURE_C55 BIT(1)
#define SYS_RZV2N_FEATURE_SEC BIT(2) #define SYS_RZV2N_FEATURE_SEC BIT(2)
#define SYS_LSI_OTPTSU0TRMVAL0 0x320
#define SYS_LSI_OTPTSU0TRMVAL1 0x324
#define SYS_LSI_OTPTSU1TRMVAL0 0x330
#define SYS_LSI_OTPTSU1TRMVAL1 0x334
#define SYS_GBETH0_CFG 0xf00
#define SYS_GBETH1_CFG 0xf04
#define SYS_PCIE_INTX_CH0 0x1000
#define SYS_PCIE_MSI1_CH0 0x1004
#define SYS_PCIE_MSI2_CH0 0x1008
#define SYS_PCIE_MSI3_CH0 0x100c
#define SYS_PCIE_MSI4_CH0 0x1010
#define SYS_PCIE_MSI5_CH0 0x1014
#define SYS_PCIE_PME_CH0 0x1018
#define SYS_PCIE_ACK_CH0 0x101c
#define SYS_PCIE_MISC_CH0 0x1020
#define SYS_PCIE_MODE_CH0 0x1024
#define SYS_ADC_CFG 0x1600
static void rzv2n_sys_print_id(struct device *dev, static void rzv2n_sys_print_id(struct device *dev,
void __iomem *sysc_base, void __iomem *sysc_base,
struct soc_device_attribute *soc_dev_attr) struct soc_device_attribute *soc_dev_attr)
@@ -70,6 +88,57 @@ static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initco
.print_id = rzv2n_sys_print_id, .print_id = rzv2n_sys_print_id,
}; };
static bool rzv2n_regmap_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_LSI_OTPTSU0TRMVAL0:
case SYS_LSI_OTPTSU0TRMVAL1:
case SYS_LSI_OTPTSU1TRMVAL0:
case SYS_LSI_OTPTSU1TRMVAL1:
case SYS_GBETH0_CFG:
case SYS_GBETH1_CFG:
case SYS_PCIE_INTX_CH0:
case SYS_PCIE_MSI1_CH0:
case SYS_PCIE_MSI2_CH0:
case SYS_PCIE_MSI3_CH0:
case SYS_PCIE_MSI4_CH0:
case SYS_PCIE_MSI5_CH0:
case SYS_PCIE_PME_CH0:
case SYS_PCIE_ACK_CH0:
case SYS_PCIE_MISC_CH0:
case SYS_PCIE_MODE_CH0:
case SYS_ADC_CFG:
return true;
default:
return false;
}
}
static bool rzv2n_regmap_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_GBETH0_CFG:
case SYS_GBETH1_CFG:
case SYS_PCIE_INTX_CH0:
case SYS_PCIE_MSI1_CH0:
case SYS_PCIE_MSI2_CH0:
case SYS_PCIE_MSI3_CH0:
case SYS_PCIE_MSI4_CH0:
case SYS_PCIE_MSI5_CH0:
case SYS_PCIE_PME_CH0:
case SYS_PCIE_ACK_CH0:
case SYS_PCIE_MISC_CH0:
case SYS_PCIE_MODE_CH0:
case SYS_ADC_CFG:
return true;
default:
return false;
}
}
const struct rz_sysc_init_data rzv2n_sys_init_data = { const struct rz_sysc_init_data rzv2n_sys_init_data = {
.soc_id_init_data = &rzv2n_sys_soc_id_init_data, .soc_id_init_data = &rzv2n_sys_soc_id_init_data,
.readable_reg = rzv2n_regmap_readable_reg,
.writeable_reg = rzv2n_regmap_writeable_reg,
.max_register = 0x170c,
}; };

101
drivers/soc/renesas/r9a09g057-sys.c
View File

@@ -29,6 +29,35 @@
#define SYS_LSI_PRR_GPU_DIS BIT(0) #define SYS_LSI_PRR_GPU_DIS BIT(0)
#define SYS_LSI_PRR_ISP_DIS BIT(4) #define SYS_LSI_PRR_ISP_DIS BIT(4)
#define SYS_LSI_OTPTSU0TRMVAL0 0x320
#define SYS_LSI_OTPTSU0TRMVAL1 0x324
#define SYS_LSI_OTPTSU1TRMVAL0 0x330
#define SYS_LSI_OTPTSU1TRMVAL1 0x334
#define SYS_GBETH0_CFG 0xf00
#define SYS_GBETH1_CFG 0xf04
#define SYS_PCIE_INTX_CH0 0x1000
#define SYS_PCIE_MSI1_CH0 0x1004
#define SYS_PCIE_MSI2_CH0 0x1008
#define SYS_PCIE_MSI3_CH0 0x100c
#define SYS_PCIE_MSI4_CH0 0x1010
#define SYS_PCIE_MSI5_CH0 0x1014
#define SYS_PCIE_PME_CH0 0x1018
#define SYS_PCIE_ACK_CH0 0x101c
#define SYS_PCIE_MISC_CH0 0x1020
#define SYS_PCIE_MODE_CH0 0x1024
#define SYS_PCIE_INTX_CH1 0x1030
#define SYS_PCIE_MSI1_CH1 0x1034
#define SYS_PCIE_MSI2_CH1 0x1038
#define SYS_PCIE_MSI3_CH1 0x103c
#define SYS_PCIE_MSI4_CH1 0x1040
#define SYS_PCIE_MSI5_CH1 0x1044
#define SYS_PCIE_PME_CH1 0x1048
#define SYS_PCIE_ACK_CH1 0x104c
#define SYS_PCIE_MISC_CH1 0x1050
#define SYS_PCIE_MODE_CH1 0x1054
#define SYS_PCIE_MODE 0x1060
#define SYS_ADC_CFG 0x1600
static void rzv2h_sys_print_id(struct device *dev, static void rzv2h_sys_print_id(struct device *dev,
void __iomem *sysc_base, void __iomem *sysc_base,
struct soc_device_attribute *soc_dev_attr) struct soc_device_attribute *soc_dev_attr)
@@ -62,7 +91,79 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initco
.print_id = rzv2h_sys_print_id, .print_id = rzv2h_sys_print_id,
}; };
static bool rzv2h_regmap_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_LSI_OTPTSU0TRMVAL0:
case SYS_LSI_OTPTSU0TRMVAL1:
case SYS_LSI_OTPTSU1TRMVAL0:
case SYS_LSI_OTPTSU1TRMVAL1:
case SYS_GBETH0_CFG:
case SYS_GBETH1_CFG:
case SYS_PCIE_INTX_CH0:
case SYS_PCIE_MSI1_CH0:
case SYS_PCIE_MSI2_CH0:
case SYS_PCIE_MSI3_CH0:
case SYS_PCIE_MSI4_CH0:
case SYS_PCIE_MSI5_CH0:
case SYS_PCIE_PME_CH0:
case SYS_PCIE_ACK_CH0:
case SYS_PCIE_MISC_CH0:
case SYS_PCIE_MODE_CH0:
case SYS_PCIE_INTX_CH1:
case SYS_PCIE_MSI1_CH1:
case SYS_PCIE_MSI2_CH1:
case SYS_PCIE_MSI3_CH1:
case SYS_PCIE_MSI4_CH1:
case SYS_PCIE_MSI5_CH1:
case SYS_PCIE_PME_CH1:
case SYS_PCIE_ACK_CH1:
case SYS_PCIE_MISC_CH1:
case SYS_PCIE_MODE_CH1:
case SYS_PCIE_MODE:
case SYS_ADC_CFG:
return true;
default:
return false;
}
}
static bool rzv2h_regmap_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_GBETH0_CFG:
case SYS_GBETH1_CFG:
case SYS_PCIE_INTX_CH0:
case SYS_PCIE_MSI1_CH0:
case SYS_PCIE_MSI2_CH0:
case SYS_PCIE_MSI3_CH0:
case SYS_PCIE_MSI4_CH0:
case SYS_PCIE_MSI5_CH0:
case SYS_PCIE_PME_CH0:
case SYS_PCIE_ACK_CH0:
case SYS_PCIE_MISC_CH0:
case SYS_PCIE_MODE_CH0:
case SYS_PCIE_INTX_CH1:
case SYS_PCIE_MSI1_CH1:
case SYS_PCIE_MSI2_CH1:
case SYS_PCIE_MSI3_CH1:
case SYS_PCIE_MSI4_CH1:
case SYS_PCIE_MSI5_CH1:
case SYS_PCIE_PME_CH1:
case SYS_PCIE_ACK_CH1:
case SYS_PCIE_MISC_CH1:
case SYS_PCIE_MODE_CH1:
case SYS_PCIE_MODE:
case SYS_ADC_CFG:
return true;
default:
return false;
}
}
const struct rz_sysc_init_data rzv2h_sys_init_data = { const struct rz_sysc_init_data rzv2h_sys_init_data = {
.soc_id_init_data = &rzv2h_sys_soc_id_init_data, .soc_id_init_data = &rzv2h_sys_soc_id_init_data,
.readable_reg = rzv2h_regmap_readable_reg,
.writeable_reg = rzv2h_regmap_writeable_reg,
.max_register = 0x170c, .max_register = 0x170c,
}; };

2
drivers/soc/renesas/rz-sysc.c
View File

@@ -140,6 +140,8 @@ static int rz_sysc_probe(struct platform_device *pdev)
regmap_cfg->val_bits = 32; regmap_cfg->val_bits = 32;
regmap_cfg->fast_io = true; regmap_cfg->fast_io = true;
regmap_cfg->max_register = data->max_register; regmap_cfg->max_register = data->max_register;
regmap_cfg->readable_reg = data->readable_reg;
regmap_cfg->writeable_reg = data->writeable_reg;
regmap = devm_regmap_init_mmio(dev, sysc->base, regmap_cfg); regmap = devm_regmap_init_mmio(dev, sysc->base, regmap_cfg);
if (IS_ERR(regmap)) if (IS_ERR(regmap))

4
drivers/soc/renesas/rz-sysc.h
View File

@@ -34,10 +34,14 @@ struct rz_sysc_soc_id_init_data {
/** /**
* struct rz_sysc_init_data - RZ SYSC initialization data * struct rz_sysc_init_data - RZ SYSC initialization data
* @soc_id_init_data: RZ SYSC SoC ID initialization data * @soc_id_init_data: RZ SYSC SoC ID initialization data
* @writeable_reg: Regmap writeable register check function
* @readable_reg: Regmap readable register check function
* @max_register: Maximum SYSC register offset to be used by the regmap config * @max_register: Maximum SYSC register offset to be used by the regmap config
*/ */
struct rz_sysc_init_data { struct rz_sysc_init_data {
const struct rz_sysc_soc_id_init_data *soc_id_init_data; const struct rz_sysc_soc_id_init_data *soc_id_init_data;
bool (*writeable_reg)(struct device *dev, unsigned int reg);
bool (*readable_reg)(struct device *dev, unsigned int reg);
u32 max_register; u32 max_register;
}; };