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scsi: ufs: host: mediatek: Add support for new platform with MMIO_OTSD_CTR

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Introduce support for a new UFS Mediatek platform by adding the
REG_UFS_UFS_MMIO_OTSD_CTRL register. This update includes checks for
legacy platforms and uses the new register to replace debug selection
and handle specific operations.  The changes ensure compatibility across
different hardware versions and prevent potential issues with debug
usage on newer platforms.

Additional updates include error logging improvements during link setup
for newer and legacy platforms, ensuring proper event logging and
debugging.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Acked-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>
Link: https://patch.msgid.link/20250924094527.2992256-8-peter.wang@mediatek.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Peter Wang
2025-09-24 17:43:29 +08:00
committed by Martin K. Petersen
parent 9b2b03b361
commit 4fb4c835a9
2 changed files with 36 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
drivers/ufs/host/ufs-mediatek.c
View File

@@ -280,6 +280,9 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,
REG_UFS_XOUFS_CTRL); REG_UFS_XOUFS_CTRL);
if (host->legacy_ip_ver)
return 0;
/* DDR_EN setting */ /* DDR_EN setting */
if (host->ip_ver >= IP_VER_MT6989) { if (host->ip_ver >= IP_VER_MT6989) {
ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8), ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8),
@@ -405,7 +408,7 @@ static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
{ {
struct ufs_mtk_host *host = ufshcd_get_variant(hba); struct ufs_mtk_host *host = ufshcd_get_variant(hba);
if (((host->ip_ver >> 16) & 0xFF) >= 0x36) { if (!host->legacy_ip_ver && host->ip_ver >= IP_VER_MT6983) {
ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL); ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0); ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1); ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
@@ -422,6 +425,7 @@ static int ufs_mtk_wait_idle_state(struct ufs_hba *hba,
u64 timeout, time_checked; u64 timeout, time_checked;
u32 val, sm; u32 val, sm;
bool wait_idle; bool wait_idle;
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
/* cannot use plain ktime_get() in suspend */ /* cannot use plain ktime_get() in suspend */
timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL; timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL;
@@ -432,8 +436,13 @@ static int ufs_mtk_wait_idle_state(struct ufs_hba *hba,
do { do {
time_checked = ktime_get_mono_fast_ns(); time_checked = ktime_get_mono_fast_ns();
ufs_mtk_dbg_sel(hba); if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) {
val = ufshcd_readl(hba, REG_UFS_PROBE); ufs_mtk_dbg_sel(hba);
val = ufshcd_readl(hba, REG_UFS_PROBE);
} else {
val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
val = val >> 16;
}
sm = val & 0x1f; sm = val & 0x1f;
@@ -465,13 +474,20 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
{ {
ktime_t timeout, time_checked; ktime_t timeout, time_checked;
u32 val; u32 val;
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
timeout = ktime_add_ms(ktime_get(), max_wait_ms); timeout = ktime_add_ms(ktime_get(), max_wait_ms);
do { do {
time_checked = ktime_get(); time_checked = ktime_get();
ufs_mtk_dbg_sel(hba);
val = ufshcd_readl(hba, REG_UFS_PROBE); if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) {
val = val >> 28; ufs_mtk_dbg_sel(hba);
val = ufshcd_readl(hba, REG_UFS_PROBE);
val = val >> 28;
} else {
val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
val = val >> 24;
}
if (val == state) if (val == state)
return 0; return 0;
@@ -1639,14 +1655,26 @@ static int ufs_mtk_device_reset(struct ufs_hba *hba)
static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
{ {
int err; int err;
u32 val;
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
err = ufshcd_hba_enable(hba); err = ufshcd_hba_enable(hba);
if (err) if (err)
return err; return err;
err = ufs_mtk_unipro_set_lpm(hba, false); err = ufs_mtk_unipro_set_lpm(hba, false);
if (err) if (err) {
if (host->ip_ver < IP_VER_MT6899) {
ufs_mtk_dbg_sel(hba);
val = ufshcd_readl(hba, REG_UFS_PROBE);
} else {
val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
}
ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)val);
val = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)val);
return err; return err;
}
err = ufshcd_uic_hibern8_exit(hba); err = ufshcd_uic_hibern8_exit(hba);
if (err) if (err)

1
drivers/ufs/host/ufs-mediatek.h
View File

@@ -28,6 +28,7 @@
*/ */
#define REG_UFS_XOUFS_CTRL 0x140 #define REG_UFS_XOUFS_CTRL 0x140
#define REG_UFS_REFCLK_CTRL 0x144 #define REG_UFS_REFCLK_CTRL 0x144
#define REG_UFS_UFS_MMIO_OTSD_CTRL 0x14C
#define REG_UFS_MMIO_OPT_CTRL_0 0x160 #define REG_UFS_MMIO_OPT_CTRL_0 0x160
#define REG_UFS_EXTREG 0x2100 #define REG_UFS_EXTREG 0x2100
#define REG_UFS_MPHYCTRL 0x2200 #define REG_UFS_MPHYCTRL 0x2200