sugar/linux
1
0
Fork 0
Code Activity

Merge tag 'tenstorrent-dt-for-v6.19' of https://github.com/tenstorrent/linux into soc/newsoc

Browse Source 
Tenstorrent device tree for v6.19

Add Tenstorrent as a vendor and enable support for the Blackhole SoC
in Blackhole P100 and P150 PCIe cards. The SoC contains four RISC-V
CPU tiles consisting of 4x SiFive X280 cores.

There is a virtual UART implemented in OpenSBI firmware that allows a
console program on the PCIe host to communicate through shared memory
with Linux running on the Blackhole card.

Link: https://github.com/tenstorrent/tt-bh-linux
Link: https://github.com/tenstorrent/opensbi/
Signed-off-by: Drew Fustini <fustini@kernel.org>

* tag 'tenstorrent-dt-for-v6.19' of https://github.com/tenstorrent/linux:
  riscv: defconfig: Enable Tenstorrent SoCs
  riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs
  riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards
  dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible
  dt-bindings: timers: Add Tenstorrent Blackhole compatible
  dt-bindings: riscv: cpus: Add SiFive X280 compatible
  dt-bindings: riscv: Add Tenstorrent Blackhole compatible
  dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC
This commit is contained in:
Arnd Bergmann
2025-11-21 16:22:33 +01:00
parent dcb6fa37fd a71e6e8eea
commit 2bab99283d
12 changed files with 176 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@@ -64,6 +64,7 @@ properties:
- spacemit,k1-plic
- starfive,jh7100-plic
- starfive,jh7110-plic
- tenstorrent,blackhole-plic
- const: sifive,plic-1.0.0
- items:
- enum:

1
Documentation/devicetree/bindings/riscv/cpus.yaml
View File

@@ -70,6 +70,7 @@ properties:
- enum:
- sifive,e51
- sifive,u54-mc
- sifive,x280
- const: sifive,rocket0
- const: riscv
- const: riscv # Simulator only

28
Documentation/devicetree/bindings/riscv/tenstorrent.yaml Normal file
View File

@@ -0,0 +1,28 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/tenstorrent.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tenstorrent SoC-based boards
maintainers:
- Drew Fustini <dfustini@oss.tenstorrent.com>
- Joel Stanley <jms@oss.tenstorrent.com>
description:
Tenstorrent SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Tenstorrent Blackhole PCIe card
items:
- const: tenstorrent,blackhole-card
- const: tenstorrent,blackhole
additionalProperties: true
...

1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
View File

@@ -36,6 +36,7 @@ properties:
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
- starfive,jh8100-clint # StarFive JH8100
- tenstorrent,blackhole-clint # Tenstorrent Blackhole
- const: sifive,clint0 # SiFive CLINT v0 IP block
- items:
- {}

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@@ -1610,6 +1610,8 @@ patternProperties:
description: Tempo Semiconductor
"^tenda,.*":
description: Shenzhen Tenda Technology Co., Ltd.
"^tenstorrent,.*":
description: Tenstorrent AI ULC
"^terasic,.*":
description: Terasic Inc.
"^tesla,.*":

9
MAINTAINERS
View File

@@ -22184,6 +22184,15 @@ F: arch/riscv/boot/dts/spacemit/
N: spacemit
K: spacemit
RISC-V TENSTORRENT SoC SUPPORT
M: Drew Fustini <dfustini@oss.tenstorrent.com>
M: Joel Stanley <jms@oss.tenstorrent.com>
L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/tenstorrent/linux.git
F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
F: arch/riscv/boot/dts/tenstorrent/
RISC-V THEAD SoC SUPPORT
M: Drew Fustini <fustini@kernel.org>
M: Guo Ren <guoren@kernel.org>

8
arch/riscv/Kconfig.socs
View File

@@ -63,6 +63,14 @@ config ARCH_SUNXI
This enables support for Allwinner sun20i platform hardware,
including boards based on the D1 and D1s SoCs.
config ARCH_TENSTORRENT
bool "Tenstorrent SoCs"
help
This enables support for Tenstorrent SoC platforms.
Current support is for Blackhole P100 and P150 PCIe cards.
The Blackhole SoC contains four RISC-V CPU tiles each
consisting of 4x SiFive X280 cores.
config ARCH_THEAD
bool "T-HEAD RISC-V SoCs"
depends on MMU && !XIP_KERNEL

1
arch/riscv/boot/dts/Makefile
View File

@@ -9,4 +9,5 @@ subdir-y += sifive
subdir-y += sophgo
subdir-y += spacemit
subdir-y += starfive
subdir-y += tenstorrent
subdir-y += thead

2
arch/riscv/boot/dts/tenstorrent/Makefile Normal file
View File

@@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb

14
arch/riscv/boot/dts/tenstorrent/blackhole-card.dts Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "blackhole.dtsi"
/ {
model = "Tenstorrent Blackhole";
compatible = "tenstorrent,blackhole-card", "tenstorrent,blackhole";
memory@400030000000 {
device_type = "memory";
reg = <0x4000 0x30000000 0x1 0x00000000>;
};
};

108
arch/riscv/boot/dts/tenstorrent/blackhole.dtsi Normal file
View File

@@ -0,0 +1,108 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
// Copyright 2025 Tenstorrent AI ULC
/dts-v1/;
/ {
compatible = "tenstorrent,blackhole";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <50000000>;
cpu@0 {
compatible = "sifive,x280", "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <0>;
mmu-type = "riscv,sv57";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@1 {
compatible = "sifive,x280", "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <1>;
mmu-type = "riscv,sv57";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@2 {
compatible = "sifive,x280", "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <2>;
mmu-type = "riscv,sv57";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@3 {
compatible = "sifive,x280", "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <3>;
mmu-type = "riscv,sv57";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
clint0: timer@2000000 {
compatible = "tenstorrent,blackhole-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>,
<&cpu1_intc 0x3>, <&cpu1_intc 0x7>,
<&cpu2_intc 0x3>, <&cpu2_intc 0x7>,
<&cpu3_intc 0x3>, <&cpu3_intc 0x7>;
};
plic0: interrupt-controller@c000000 {
compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0";
reg = <0x0 0x0c000000 0x0 0x04000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <0>;
riscv,ndev = <128>;
};
};
};

1
arch/riscv/configs/defconfig
View File

@@ -29,6 +29,7 @@ CONFIG_ARCH_SOPHGO=y
CONFIG_ARCH_SPACEMIT=y
CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_TENSTORRENT=y
CONFIG_ARCH_THEAD=y
CONFIG_ARCH_VIRT=y
CONFIG_ARCH_CANAAN=y