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scsi: ufs: host: mediatek: Handle clock scaling for high gear in PM flow

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Add clock scaling down for power management flow in the UFS Mediatek
driver. If clock scaling is disabled and fixed in high gear, ensure the
clock scales down during suspend and scales up again after resume to
support high gear.  This adjustment maintains proper power management.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Acked-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>
Link: https://patch.msgid.link/20250924094527.2992256-4-peter.wang@mediatek.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Peter Wang
2025-09-24 17:43:25 +08:00
committed by Martin K. Petersen
parent 55ce691dc7
commit 16b42c4281
1 changed files with 6 additions and 0 deletions
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6
drivers/ufs/host/ufs-mediatek.c
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@@ -1778,6 +1778,9 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) {
ufshcd_pm_qos_update(hba, false);
_ufs_mtk_clk_scale(hba, false);
} else if ((!ufshcd_is_clkscaling_supported(hba) &&
hba->pwr_info.gear_rx >= UFS_HS_G5)) {
_ufs_mtk_clk_scale(hba, false);
}
return 0;
@@ -1810,6 +1813,9 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) {
ufshcd_pm_qos_update(hba, true);
_ufs_mtk_clk_scale(hba, true);
} else if ((!ufshcd_is_clkscaling_supported(hba) &&
hba->pwr_info.gear_rx >= UFS_HS_G5)) {
_ufs_mtk_clk_scale(hba, true);
}
if (ufshcd_is_link_hibern8(hba)) {